Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/137187/?format=api
{ "id": 137187, "url": "http://patches.dpdk.org/api/patches/137187/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240226030739.3775514-7-haijie1@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240226030739.3775514-7-haijie1@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240226030739.3775514-7-haijie1@huawei.com", "date": "2024-02-26T03:07:38", "name": "[v4,6/7] net/hns3: support filter directly accessed registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2a430627807ae50bb5c8b58efbb222457d280f20", "submitter": { "id": 2935, "url": "http://patches.dpdk.org/api/people/2935/?format=api", "name": "Jie Hai", "email": "haijie1@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240226030739.3775514-7-haijie1@huawei.com/mbox/", "series": [ { "id": 31212, "url": "http://patches.dpdk.org/api/series/31212/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31212", "date": "2024-02-26T03:07:32", "name": "support dump reigser names and filter them", "version": 4, "mbox": "http://patches.dpdk.org/series/31212/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137187/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137187/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BC6C243BDE;\n\tMon, 26 Feb 2024 04:12:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 13D4842DD6;\n\tMon, 26 Feb 2024 04:12:07 +0100 (CET)", "from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35])\n by mails.dpdk.org (Postfix) with ESMTP id 2C23542D8C\n for <dev@dpdk.org>; Mon, 26 Feb 2024 04:11:57 +0100 (CET)", "from mail.maildlp.com (unknown [172.19.88.214])\n by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Tjlw62tb0z1X3PL;\n Mon, 26 Feb 2024 11:09:42 +0800 (CST)", "from kwepemd100004.china.huawei.com (unknown [7.221.188.31])\n by mail.maildlp.com (Postfix) with ESMTPS id B083C1A016B;\n Mon, 26 Feb 2024 11:11:55 +0800 (CST)", "from localhost.localdomain (10.67.165.2) by\n kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.2.1258.28; Mon, 26 Feb 2024 11:11:55 +0800" ], "From": "Jie Hai <haijie1@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<lihuisong@huawei.com>, <fengchengwen@huawei.com>,\n <liuyonglong@huawei.com>, <huangdengdui@huawei.com>, <ferruh.yigit@amd.com>", "Subject": "[PATCH v4 6/7] net/hns3: support filter directly accessed registers", "Date": "Mon, 26 Feb 2024 11:07:38 +0800", "Message-ID": "<20240226030739.3775514-7-haijie1@huawei.com>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20240226030739.3775514-1-haijie1@huawei.com>", "References": "<20231214015650.3738578-1-haijie1@huawei.com>\n <20240226030739.3775514-1-haijie1@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.2]", "X-ClientProxiedBy": "dggems705-chm.china.huawei.com (10.3.19.182) To\n kwepemd100004.china.huawei.com (7.221.188.31)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch supports reporting names of registers which\ncan be directly accessed by addresses and filtering\nthem by names.\n\nSigned-off-by: Jie Hai <haijie1@huawei.com>\n---\n drivers/net/hns3/hns3_regs.c | 198 +++++++++++++++++++++++++++++------\n 1 file changed, 167 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c\nindex b7e4f78eecde..7c3bd162f067 100644\n--- a/drivers/net/hns3/hns3_regs.c\n+++ b/drivers/net/hns3/hns3_regs.c\n@@ -837,8 +837,24 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,\n \treturn 0;\n }\n \n+static uint32_t\n+hns3_get_direct_regs_cnt(const struct direct_reg_list *list,\n+\t\t\t uint32_t len, const char *filter)\n+{\n+\tuint32_t i;\n+\tuint32_t count = 0;\n+\n+\tfor (i = 0 ; i < len; i++) {\n+\t\tif (filter != NULL && !strstr(list[i].name, filter))\n+\t\t\tcontinue;\n+\t\tcount++;\n+\t}\n+\n+\treturn count;\n+}\n+\n static int\n-hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)\n+hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, const char *filter)\n {\n \tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n \tuint32_t cmdq_cnt, common_cnt, ring_cnt, tqp_intr_cnt;\n@@ -847,13 +863,18 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)\n \tuint32_t len;\n \tint ret;\n \n-\tcmdq_cnt = RTE_DIM(cmdq_reg_list);\n+\tcmdq_cnt = hns3_get_direct_regs_cnt(cmdq_reg_list,\n+\t\t\t\t\t RTE_DIM(cmdq_reg_list), filter);\n \tif (hns->is_vf)\n-\t\tcommon_cnt = sizeof(common_vf_reg_list);\n+\t\tcommon_cnt = hns3_get_direct_regs_cnt(common_vf_reg_list,\n+\t\t\t\t\tRTE_DIM(common_vf_reg_list), filter);\n \telse\n-\t\tcommon_cnt = RTE_DIM(common_reg_list);\n-\tring_cnt = RTE_DIM(ring_reg_list);\n-\ttqp_intr_cnt = RTE_DIM(tqp_intr_reg_list);\n+\t\tcommon_cnt = hns3_get_direct_regs_cnt(common_reg_list,\n+\t\t\t\t\tRTE_DIM(common_reg_list), filter);\n+\tring_cnt = hns3_get_direct_regs_cnt(ring_reg_list,\n+\t\t\t\t\t RTE_DIM(ring_reg_list), filter);\n+\ttqp_intr_cnt = hns3_get_direct_regs_cnt(tqp_intr_reg_list,\n+\t\t\t\t\tRTE_DIM(tqp_intr_reg_list), filter);\n \n \tlen = cmdq_cnt + common_cnt + ring_cnt * hw->tqps_num +\n \t tqp_intr_cnt * hw->intr_tqps_num;\n@@ -995,47 +1016,160 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n \treturn 0;\n }\n \n-static int\n-hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)\n+\n+static uint32_t\n+hns3_direct_access_cmdq_reg(struct hns3_hw *hw,\n+\t\t\t struct rte_dev_reg_info *regs,\n+\t\t\t uint32_t count)\n {\n-\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n-\tuint32_t *origin_data_ptr = data;\n-\tuint32_t reg_offset;\n+\tuint32_t *data = regs->data;\n \tsize_t reg_num;\n-\tuint16_t j;\n+\tdata += count;\n \tsize_t i;\n \n-\t/* fetching per-PF registers values from PF PCIe register space */\n \treg_num = RTE_DIM(cmdq_reg_list);\n-\tfor (i = 0; i < reg_num; i++)\n+\tfor (i = 0; i < reg_num; i++) {\n+\t\tif (regs->filter != NULL &&\n+\t\t\t!strstr(cmdq_reg_list[i].name, regs->filter))\n+\t\t\tcontinue;\n \t\t*data++ = hns3_read_dev(hw, cmdq_reg_list[i].addr);\n+\t\tif (regs->names == NULL)\n+\t\t\tcontinue;\n+\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t \"%s\", cmdq_reg_list[i].name);\n+\t}\n \n-\tif (hns->is_vf)\n-\t\treg_num = RTE_DIM(common_vf_reg_list);\n-\telse\n-\t\treg_num = RTE_DIM(common_reg_list);\n-\tfor (i = 0; i < reg_num; i++)\n-\t\tif (hns->is_vf)\n-\t\t\t*data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr);\n-\t\telse\n-\t\t\t*data++ = hns3_read_dev(hw, common_reg_list[i].addr);\n+\treturn count;\n+}\n+static uint32_t\n+hns3_direct_access_common_reg(struct hns3_hw *hw,\n+\t\t\t struct rte_dev_reg_info *regs,\n+\t\t\t uint32_t count)\n+{\n+\tuint32_t *data = regs->data;\n+\tsize_t reg_num;\n+\tdata += count;\n+\tsize_t i;\n \n+\treg_num = RTE_DIM(common_reg_list);\n+\tfor (i = 0; i < reg_num; i++) {\n+\t\tif (regs->filter != NULL &&\n+\t\t\t!strstr(common_reg_list[i].name, regs->filter))\n+\t\t\tcontinue;\n+\t\t*data++ = hns3_read_dev(hw, common_reg_list[i].addr);\n+\t\tif (regs->names == NULL)\n+\t\t\tcontinue;\n+\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t \"%s\", common_reg_list[i].name);\n+\t}\n+\n+\treturn count;\n+}\n+\n+static uint32_t\n+hns3_direct_access_vf_common_reg(struct hns3_hw *hw,\n+\t\t\t\t struct rte_dev_reg_info *regs,\n+\t\t\t\t uint32_t count)\n+{\n+\tuint32_t *data = regs->data;\n+\tsize_t reg_num;\n+\tdata += count;\n+\tsize_t i;\n+\n+\treg_num = RTE_DIM(common_vf_reg_list);\n+\tfor (i = 0; i < reg_num; i++) {\n+\t\tif (regs->filter != NULL &&\n+\t\t\t!strstr(common_vf_reg_list[i].name, regs->filter))\n+\t\t\tcontinue;\n+\t\t*data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr);\n+\t\tif (regs->names == NULL)\n+\t\t\tcontinue;\n+\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t \"%s\", common_vf_reg_list[i].name);\n+\t}\n+\n+\treturn count;\n+}\n+\n+static uint32_t\n+hns3_direct_access_ring_reg(struct hns3_hw *hw,\n+\t\t\t struct rte_dev_reg_info *regs,\n+\t\t\t uint32_t count)\n+{\n+\tuint32_t *data = regs->data;\n+\tuint32_t reg_offset;\n+\tsize_t reg_num;\n+\tuint16_t j;\n+\tsize_t i;\n+\n+\tdata += count;\n \treg_num = RTE_DIM(ring_reg_list);\n \tfor (j = 0; j < hw->tqps_num; j++) {\n \t\treg_offset = hns3_get_tqp_reg_offset(j);\n-\t\tfor (i = 0; i < reg_num; i++)\n-\t\t\t*data++ = hns3_read_dev(hw,\n-\t\t\t\t\t\tring_reg_list[i].addr + reg_offset);\n+\t\tfor (i = 0; i < reg_num; i++) {\n+\t\t\tif (regs->filter != NULL &&\n+\t\t\t\t!strstr(ring_reg_list[i].name, regs->filter))\n+\t\t\t\tcontinue;\n+\t\t\t*data++ = hns3_read_dev(hw, ring_reg_list[i].addr +\n+\t\t\t\t\t\t reg_offset);\n+\t\t\tif (regs->names == NULL)\n+\t\t\t\tcontinue;\n+\t\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t\t\"queue_%u_%s\", j, ring_reg_list[i].name);\n+\t\t}\n \t}\n \n+\treturn count;\n+}\n+\n+static uint32_t\n+hns3_direct_access_tqp_intr_reg(struct hns3_hw *hw,\n+\t\t\t struct rte_dev_reg_info *regs,\n+\t\t\t uint32_t count)\n+{\n+\tuint32_t *data = regs->data;\n+\tuint32_t reg_offset;\n+\tsize_t reg_num;\n+\tuint16_t j;\n+\tsize_t i;\n+\n+\tdata += count;\n \treg_num = RTE_DIM(tqp_intr_reg_list);\n \tfor (j = 0; j < hw->intr_tqps_num; j++) {\n \t\treg_offset = hns3_get_tqp_intr_reg_offset(j);\n-\t\tfor (i = 0; i < reg_num; i++)\n+\t\tfor (i = 0; i < reg_num; i++) {\n+\t\t\tif (regs->filter != NULL &&\n+\t\t\t\t!strstr(tqp_intr_reg_list[i].name, regs->filter))\n+\t\t\t\tcontinue;\n \t\t\t*data++ = hns3_read_dev(hw, tqp_intr_reg_list[i].addr +\n \t\t\t\t\t\treg_offset);\n+\t\t\tif (regs->names == NULL)\n+\t\t\t\tcontinue;\n+\t\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t\t\"queue_%u_%s\", j, tqp_intr_reg_list[i].name);\n+\t\t}\n \t}\n-\treturn data - origin_data_ptr;\n+\n+\treturn count;\n+}\n+\n+static uint32_t\n+hns3_direct_access_regs(struct hns3_hw *hw,\n+\t\t\tstruct rte_dev_reg_info *regs,\n+\t\t\tuint32_t count)\n+{\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\n+\tcount = hns3_direct_access_cmdq_reg(hw, regs, count);\n+\tif (!hns->is_vf)\n+\t\tcount = hns3_direct_access_common_reg(hw, regs, count);\n+\telse\n+\t\tcount = hns3_direct_access_vf_common_reg(hw, regs, count);\n+\n+\tcount = hns3_direct_access_ring_reg(hw, regs, count);\n+\tcount = hns3_direct_access_tqp_intr_reg(hw, regs, count);\n+\n+\treturn count;\n }\n \n static int\n@@ -1177,11 +1311,12 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n \tstruct hns3_hw *hw = &hns->hw;\n \tuint32_t regs_num_32_bit;\n \tuint32_t regs_num_64_bit;\n+\tuint32_t count = 0;\n \tuint32_t length;\n \tuint32_t *data;\n \tint ret;\n \n-\tret = hns3_get_regs_length(hw, &length);\n+\tret = hns3_get_regs_length(hw, &length, regs->filter);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1193,13 +1328,14 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n \t}\n \n \t/* Only full register dump is supported */\n-\tif (regs->length && regs->length != length)\n+\tif ((regs->length && regs->length != length))\n \t\treturn -ENOTSUP;\n \n \tregs->version = hw->fw_version;\n \n \t/* fetching per-PF registers values from PF PCIe register space */\n-\tdata += hns3_direct_access_regs(hw, data);\n+\tcount = hns3_direct_access_regs(hw, regs, count);\n+\tdata += count;\n \n \tif (hns->is_vf)\n \t\treturn 0;\n", "prefixes": [ "v4", "6/7" ] }