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GET /api/patches/137100/?format=api
{ "id": 137100, "url": "http://patches.dpdk.org/api/patches/137100/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240223142320.49470-2-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240223142320.49470-2-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240223142320.49470-2-dsosnowski@nvidia.com", "date": "2024-02-23T14:23:17", "name": "[v2,1/4] net/mlx5: fix conntrack action handle representation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7754fa8d8cee683ee01f4700cdb37ae7ec696972", "submitter": { "id": 2386, "url": "http://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240223142320.49470-2-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 31203, "url": "http://patches.dpdk.org/api/series/31203/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31203", "date": "2024-02-23T14:23:16", "name": "net/mlx5: connection tracking changes", "version": 2, "mbox": "http://patches.dpdk.org/series/31203/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137100/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/137100/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 20D2643BA9;\n\tFri, 23 Feb 2024 15:24:05 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D74AB40E36;\n\tFri, 23 Feb 2024 15:24:04 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id AE2704021E;\n Fri, 23 Feb 2024 15:24:02 +0100 (CET)", "from SJ0PR05CA0027.namprd05.prod.outlook.com (2603:10b6:a03:33b::32)\n by SN7PR12MB7833.namprd12.prod.outlook.com (2603:10b6:806:344::15)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.24; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Alexander Kozyrev <akozyrev@nvidia.com>", "CC": "<dev@dpdk.org>, <stable@dpdk.org>", "Subject": "[PATCH v2 1/4] net/mlx5: fix conntrack action handle representation", "Date": "Fri, 23 Feb 2024 16:23:17 +0200", "Message-ID": "<20240223142320.49470-2-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240223142320.49470-1-dsosnowski@nvidia.com>", "References": "<20240221100145.8234-1-dsosnowski@nvidia.com>\n <20240223142320.49470-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS3PEPF000099DD:EE_|SN7PR12MB7833:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c3eadb04-e588-4ec3-49db-08dc347b13c4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n a8bBwWlAXTjk+0u1BPj6vSycNnzJb59R0o24wsEOttlDWNfCgNMaSM74d0Il3i53prIpPxcXYDJyjz/ytjM/bVHl9fDhdN3jIxP0QSum2oWQp/KOS7EHXD/t8SVyjz9SpHyn2RU0GYjzpcQwvnHy6zDdDrDP6IkEhIGYgUg8rsftUuDHAg/eadE5eI/iaGnHxhltCz6XkI2tzO6PDv4JVdaJ6qCKO326PcA3gPAuYB8ZIIXIn2UMZf0TCwJQEu1JK76CoD1uw8DdiJVr5Z6zSN8tLmi/CuoU7y1M8vRUN4VDuaWI4MA6TnFx5bsJcCNOEpcbKPnu0qpiu9N555ZjursDh858or07uQMgMu5kbDOqWYYQGeaHmNlv5h1U5HUp9U156rSmHvW2GuUdMHS/rA24po9u4ELkI1fm/F/fD389nmEBtXpq5MqfZ/xuwnhNviT8Dup/9G6Ak6DjOo/HDEKBMzza24SQdr9AAWUO/crXnadG5JKwM1Ge/FFOncGh+zgIZ9thj0yiPuVGf7ppHK4Dn8ljlx6Mjea5c9cnMCo17cqbVDDUuVChlHNfIK+esMTur79Si+Z0uKQ9erp7tzw/DgHbMEy9gPosAR+5S+F+W31XMxAI6L9l9Slndp+9urK7ik6GgSuHB8wMBEhH/Kbj4WND1fPX7Cl+qKUtTt0=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004)(40470700004)(46966006); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Feb 2024 14:23:59.4051 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c3eadb04-e588-4ec3-49db-08dc347b13c4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS3PEPF000099DD.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7833", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In mlx5 PMD, handles to indirect connection tracking flow actions\nare encoded in 32-bit unsigned integers as follows:\n\n- Bits 31-29 - indirect action type.\n- Bits 28-25 - port on which connection tracking action was created.\n- Bits 24-0 - index of connection tracking object.\n\nMacro defining a bit shift for owner part in this representation\nwas incorrectly defined as 22. This patch fixes that, as well as\naligns documented limitations.\n\nFixes: 463170a7c934 (\"net/mlx5: support connection tracking with HWS\")\nFixes: 48fbb0e93d06 (\"net/mlx5: support flow meter mark indirect action with HWS\")\nCc: stable@dpdk.org\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 4 ++--\n drivers/net/mlx5/mlx5_flow.h | 2 +-\n 2 files changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 0d2213497a..90ae3f3047 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -783,8 +783,8 @@ Limitations\n \n - Cannot co-exist with ASO meter, ASO age action in a single flow rule.\n - Flow rules insertion rate and memory consumption need more optimization.\n- - 256 ports maximum.\n- - 4M connections maximum with ``dv_flow_en`` 1 mode. 16M with ``dv_flow_en`` 2.\n+ - 16 ports maximum.\n+ - 32M connections maximum.\n \n - Multi-thread flow insertion:\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex a4d0ff7b13..b4bf96cd64 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -77,7 +77,7 @@ enum mlx5_indirect_type {\n /* Now, the maximal ports will be supported is 16, action number is 32M. */\n #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x10\n \n-#define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22\n+#define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 25\n #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)\n \n /* 29-31: type, 25-28: owner port, 0-24: index */\n", "prefixes": [ "v2", "1/4" ] }