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GET /api/patches/136903/?format=api
{ "id": 136903, "url": "http://patches.dpdk.org/api/patches/136903/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240220105823.570841-8-haijie1@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240220105823.570841-8-haijie1@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240220105823.570841-8-haijie1@huawei.com", "date": "2024-02-20T10:58:23", "name": "[v3,7/7] net/hns3: support filter dump of registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "23ecd28f3bf1ea8bb7f5f77fb1ad3fce329de353", "submitter": { "id": 2935, "url": "http://patches.dpdk.org/api/people/2935/?format=api", "name": "Jie Hai", "email": "haijie1@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240220105823.570841-8-haijie1@huawei.com/mbox/", "series": [ { "id": 31148, "url": "http://patches.dpdk.org/api/series/31148/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31148", "date": "2024-02-20T10:58:16", "name": "support dump reigser names and filter them", "version": 3, "mbox": "http://patches.dpdk.org/series/31148/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136903/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/136903/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9027143B53;\n\tTue, 20 Feb 2024 12:03:33 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C40014111C;\n\tTue, 20 Feb 2024 12:02:45 +0100 (CET)", "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by mails.dpdk.org (Postfix) with ESMTP id 7EB6340EF1\n for <dev@dpdk.org>; Tue, 20 Feb 2024 12:02:39 +0100 (CET)", "from mail.maildlp.com (unknown [172.19.163.17])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4TfGg06JF6z1xp8h;\n Tue, 20 Feb 2024 19:01:16 +0800 (CST)", "from kwepemd100004.china.huawei.com (unknown [7.221.188.31])\n by mail.maildlp.com (Postfix) with ESMTPS id 68B801A0172;\n Tue, 20 Feb 2024 19:02:38 +0800 (CST)", "from localhost.localdomain (10.67.165.2) by\n kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.2.1258.28; Tue, 20 Feb 2024 19:02:37 +0800" ], "From": "Jie Hai <haijie1@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<lihuisong@huawei.com>, <fengchengwen@huawei.com>,\n <liuyonglong@huawei.com>, <huangdengdui@huawei.com>, <ferruh.yigit@amd.com>", "Subject": "[PATCH v3 7/7] net/hns3: support filter dump of registers", "Date": "Tue, 20 Feb 2024 18:58:23 +0800", "Message-ID": "<20240220105823.570841-8-haijie1@huawei.com>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20240220105823.570841-1-haijie1@huawei.com>", "References": "<20231214015650.3738578-1-haijie1@huawei.com>\n <20240220105823.570841-1-haijie1@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.2]", "X-ClientProxiedBy": "dggems706-chm.china.huawei.com (10.3.19.183) To\n kwepemd100004.china.huawei.com (7.221.188.31)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch supports reporting names of the dfx registers\nwhich filtering them by names.\n\nSigned-off-by: Jie Hai <haijie1@huawei.com>\n---\n drivers/net/hns3/hns3_regs.c | 277 +++++++++++++++++++++++++++++------\n 1 file changed, 230 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c\nindex 3e3d0326260d..ae451dc14a2e 100644\n--- a/drivers/net/hns3/hns3_regs.c\n+++ b/drivers/net/hns3/hns3_regs.c\n@@ -12,7 +12,8 @@\n \n #define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t))\n \n-static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count);\n+static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw,\n+\t\t\t\tuint32_t *count, char *filter);\n \n struct direct_reg_list {\n \tconst char *name;\n@@ -853,12 +854,41 @@ hns3_get_direct_regs_cnt(const struct direct_reg_list *list,\n \treturn count;\n }\n \n+static uint32_t\n+hns3_get_32_64_regs_cnt(struct hns3_hw *hw, char *filter)\n+{\n+\tuint32_t regs_num_32_bit, regs_num_64_bit;\n+\tint ret;\n+\tuint32_t i;\n+\tuint32_t count = 0;\n+\n+\tret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to get the number of registers, \"\n+\t\t\t \"ret = %d.\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0 ; i < regs_num_32_bit; i++) {\n+\t\tif (filter != NULL &&\n+\t\t\t!strstr(regs_32_bit_list[i].new_name, filter))\n+\t\t\tcontinue;\n+\t\tcount++;\n+\t}\n+\tfor (i = 0 ; i < regs_num_64_bit * HNS3_64_BIT_REG_SIZE; i++) {\n+\t\tif (filter != NULL &&\n+\t\t\t!strstr(regs_64_bit_list[i].new_name, filter))\n+\t\t\tcontinue;\n+\t\tcount++;\n+\t}\n+\treturn count;\n+}\n+\n static int\n hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, char *filter)\n {\n \tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n \tuint32_t cmdq_cnt, common_cnt, ring_cnt, tqp_intr_cnt;\n-\tuint32_t regs_num_32_bit, regs_num_64_bit;\n \tuint32_t dfx_reg_cnt;\n \tuint32_t len;\n \tint ret;\n@@ -880,16 +910,9 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, char *filter)\n \t tqp_intr_cnt * hw->intr_tqps_num;\n \n \tif (!hns->is_vf) {\n-\t\tret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);\n-\t\tif (ret) {\n-\t\t\thns3_err(hw, \"fail to get the number of registers, \"\n-\t\t\t\t \"ret = %d.\", ret);\n-\t\t\treturn ret;\n-\t\t}\n-\t\tdfx_reg_cnt = regs_num_32_bit +\n-\t\t\t regs_num_64_bit * HNS3_64_BIT_REG_SIZE;\n+\t\tdfx_reg_cnt = hns3_get_32_64_regs_cnt(hw, filter);\n \n-\t\tret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt);\n+\t\tret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt, filter);\n \t\tif (ret) {\n \t\t\thns3_err(hw, \"fail to get the number of dfx registers, \"\n \t\t\t\t \"ret = %d.\", ret);\n@@ -903,19 +926,19 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length, char *filter)\n }\n \n static int\n-hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n+hns3_get_32_bit_regs(struct hns3_hw *hw, void *data)\n {\n #define HNS3_32_BIT_REG_RTN_DATANUM 8\n #define HNS3_32_BIT_DESC_NODATA_LEN 2\n \tstruct hns3_cmd_desc *desc;\n \tuint32_t *reg_val = data;\n \tuint32_t *desc_data;\n+\tuint32_t regs_num;\n \tint cmd_num;\n \tint i, k, n;\n \tint ret;\n \n-\tif (regs_num == 0)\n-\t\treturn 0;\n+\tregs_num = RTE_DIM(regs_32_bit_list);\n \n \tcmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,\n \t\t\t HNS3_32_BIT_REG_RTN_DATANUM);\n@@ -959,20 +982,68 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n \treturn 0;\n }\n \n+static void\n+hns3_filter_32_bit_regs(struct rte_dev_reg_info *regs,\n+\t\t\tuint32_t *count, uint32_t *data)\n+{\n+\tuint32_t *regs_data;\n+\tregs_data = regs->data;\n+\tregs_data += *count;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < RTE_DIM(regs_32_bit_list); i++) {\n+\t\tif (regs->filter != NULL &&\n+\t\t\t!strstr(regs_32_bit_list[i].new_name, regs->filter)) {\n+\t\t\tdata++;\n+\t\t\tcontinue;\n+\t\t}\n+\t\t*regs_data++ = *data++;\n+\t\tif (regs->names == NULL)\n+\t\t\tcontinue;\n+\t\tsnprintf(regs->names[(*count)++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t \"%s\", regs_32_bit_list[i].new_name);\n+\t}\n+}\n+\n+static int\n+hns3_get_32_bit_regs_filtered(struct hns3_hw *hw,\n+\t\t\tstruct rte_dev_reg_info *regs, uint32_t *count)\n+{\n+\tuint32_t *data;\n+\tint ret;\n+\n+\tif (count == NULL)\n+\t\treturn -EINVAL;\n+\n+\tdata = rte_zmalloc(NULL, sizeof(uint32_t) * RTE_DIM(regs_32_bit_list), 0);\n+\tif (data == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tret = hns3_get_32_bit_regs(hw, data);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Get 32 bit register failed, ret = %d\", ret);\n+\t\trte_free(data);\n+\t\treturn ret;\n+\t}\n+\n+\thns3_filter_32_bit_regs(regs, count, data);\n+\treturn 0;\n+}\n+\n static int\n-hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n+hns3_get_64_bit_regs(struct hns3_hw *hw, void *data)\n {\n #define HNS3_64_BIT_REG_RTN_DATANUM 4\n #define HNS3_64_BIT_DESC_NODATA_LEN 1\n \tstruct hns3_cmd_desc *desc;\n \tuint64_t *reg_val = data;\n \tuint64_t *desc_data;\n+\tuint32_t regs_num;\n \tint cmd_num;\n \tint i, k, n;\n \tint ret;\n \n-\tif (regs_num == 0)\n-\t\treturn 0;\n+\tregs_num = RTE_DIM(regs_64_bit_list);\n \n \tcmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,\n \t\t\t HNS3_64_BIT_REG_RTN_DATANUM);\n@@ -1016,6 +1087,54 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n \treturn 0;\n }\n \n+static void\n+hns3_filter_64_bit_regs(struct rte_dev_reg_info *regs,\n+\t\t\tuint32_t *count, uint32_t *data)\n+{\n+\tuint32_t *regs_data;\n+\tregs_data = regs->data;\n+\tregs_data += *count;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < RTE_DIM(regs_64_bit_list); i++) {\n+\t\tif (regs->filter != NULL &&\n+\t\t\t!strstr(regs_64_bit_list[i].new_name, regs->filter)) {\n+\t\t\tdata++;\n+\t\t\tcontinue;\n+\t\t}\n+\t\t*regs_data++ = *data++;\n+\t\tif (regs->names == NULL)\n+\t\t\tcontinue;\n+\t\tsnprintf(regs->names[(*count)++].name, RTE_ETH_REG_NAME_SIZE,\n+\t\t\t \"%s\", regs_64_bit_list[i].new_name);\n+\t}\n+}\n+\n+static int\n+hns3_get_64_bit_regs_filtered(struct hns3_hw *hw,\n+\t\t\t struct rte_dev_reg_info *regs, uint32_t *count)\n+{\n+\tuint32_t *data;\n+\tint ret = 0;\n+\n+\tif (count == NULL)\n+\t\treturn -EINVAL;\n+\n+\tdata = rte_zmalloc(NULL, sizeof(uint32_t) * RTE_DIM(regs_64_bit_list), 0);\n+\tif (data == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tret = hns3_get_64_bit_regs(hw, data);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Get 64 bit register failed, ret = %d\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\thns3_filter_64_bit_regs(regs, count, data);\n+out:\n+\trte_free(data);\n+\treturn 0;\n+}\n \n static uint32_t\n hns3_direct_access_cmdq_reg(struct hns3_hw *hw,\n@@ -1115,7 +1234,7 @@ hns3_direct_access_ring_reg(struct hns3_hw *hw,\n \t\t\tif (regs->names == NULL)\n \t\t\t\tcontinue;\n \t\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n-\t\t\t\t\"queue_%u_%s\", j, ring_reg_list[i].name);\n+\t\t\t\t \"queue_%u_%s\", j, ring_reg_list[i].name);\n \t\t}\n \t}\n \n@@ -1146,7 +1265,7 @@ hns3_direct_access_tqp_intr_reg(struct hns3_hw *hw,\n \t\t\tif (regs->names == NULL)\n \t\t\t\tcontinue;\n \t\t\tsnprintf(regs->names[count++].name, RTE_ETH_REG_NAME_SIZE,\n-\t\t\t\t\"queue_%u_%s\", j, tqp_intr_reg_list[i].name);\n+\t\t\t\t \"queue_%u_%s\", j, tqp_intr_reg_list[i].name);\n \t\t}\n \t}\n \n@@ -1248,31 +1367,48 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg)\n }\n \n static int\n-hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count)\n+hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count, char *filter)\n {\n \tint opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);\n+\tuint32_t bd_num, data_len, reg_num = 0;\n+\tconst struct hns3_reg_entry *regs;\n \tuint32_t bd_num_list[opcode_num];\n+\tuint32_t i, j;\n \tint ret;\n-\tint i;\n \n \tret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num);\n \tif (ret)\n \t\treturn ret;\n \n-\tfor (i = 0; i < opcode_num; i++)\n-\t\t*count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM;\n+\tfor (i = 0; i < (uint32_t)opcode_num; i++) {\n+\t\tbd_num = bd_num_list[i];\n+\t\tdata_len = bd_num * HNS3_CMD_DESC_DATA_NUM;\n+\t\tif (data_len != hns3_dfx_reg_list[i].entry_num) {\n+\t\t\thns3_err(hw, \"The number of registers(%u) diff from registers list(%u)!\\n\",\n+\t\t\t\t data_len, hns3_dfx_reg_list[i].entry_num);\n+\t\t\treturn -EINVAL;\n+\t\t}\n \n+\t\tregs = hns3_dfx_reg_list[i].regs;\n+\t\tfor (j = 0; j < data_len; j++) {\n+\t\t\tif (filter != NULL &&\n+\t\t\t\t!strstr(regs[j].new_name, filter))\n+\t\t\t\tcontinue;\n+\t\t\treg_num++;\n+\t\t}\n+\t}\n+\n+\t*count += reg_num;\n \treturn 0;\n }\n \n static int\n-hns3_get_dfx_regs(struct hns3_hw *hw, void **data)\n+hns3_get_dfx_regs(struct hns3_hw *hw, uint32_t *data)\n {\n \tint opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);\n \tuint32_t max_bd_num, bd_num, opcode;\n \tuint32_t bd_num_list[opcode_num];\n \tstruct hns3_cmd_desc *cmd_descs;\n-\tuint32_t *reg_val = (uint32_t *)*data;\n \tint ret;\n \tint i;\n \n@@ -1296,32 +1432,87 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data)\n \t\tret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode);\n \t\tif (ret)\n \t\t\tbreak;\n-\t\treg_val += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, reg_val);\n+\t\tdata += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data);\n \t}\n \trte_free(cmd_descs);\n-\t*data = (void *)reg_val;\n \n \treturn ret;\n }\n \n+static void\n+hns3_filter_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs,\n+\t\t uint32_t *count, uint32_t *data)\n+{\n+\tuint32_t *regs_data = regs->data;\n+\tconst char *name = NULL;\n+\tuint32_t i, j, cnt;\n+\n+\tcnt = *count;\n+\tregs_data += cnt;\n+\tfor (i = 0; i < RTE_DIM(hns3_dfx_reg_list); i++) {\n+\t\tfor (j = 0; j < hns3_dfx_reg_list[i].entry_num; j++) {\n+\t\t\tif (hw->revision < PCI_REVISION_ID_HIP09_A &&\n+\t\t\t\thns3_dfx_reg_list[i].regs[j].old_name != NULL)\n+\t\t\t\tname = hns3_dfx_reg_list[i].regs[j].old_name;\n+\t\t\telse\n+\t\t\t\tname = hns3_dfx_reg_list[i].regs[j].new_name;\n+\n+\t\t\tif (regs->filter != NULL && !strstr(name, regs->filter)) {\n+\t\t\t\tdata++;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\t*regs_data++ = *data++;\n+\n+\t\t\tif (regs->names == NULL)\n+\t\t\t\tcontinue;\n+\t\t\tsnprintf(regs->names[cnt++].name,\n+\t\t\t\t RTE_ETH_REG_NAME_SIZE, \"%s\", name);\n+\t\t}\n+\t}\n+\t*count = cnt;\n+}\n+\n+static int\n+hns3_get_dfx_regs_filtered(struct hns3_hw *hw, struct rte_dev_reg_info *regs,\n+\t\t\t uint32_t *count)\n+{\n+\tuint32_t reg_num = 0;\n+\tuint32_t *data;\n+\tuint32_t i;\n+\tint ret;\n+\n+\tfor (i = 0; i < RTE_DIM(hns3_dfx_reg_list); i++)\n+\t\treg_num += hns3_dfx_reg_list[i].entry_num;\n+\n+\tdata = rte_zmalloc(NULL, sizeof(uint32_t) * reg_num, 0);\n+\tif (data == NULL) {\n+\t\thns3_err(hw, \"No memory for dfx regs!\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tret = hns3_get_dfx_regs(hw, data);\n+\tif (ret != 0)\n+\t\tgoto out;\n+\n+\thns3_filter_dfx_regs(hw, regs, count, data);\n+out:\n+\trte_free(data);\n+\treturn ret;\n+}\n+\n int\n hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n {\n \tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n \tstruct hns3_hw *hw = &hns->hw;\n-\tuint32_t regs_num_32_bit;\n-\tuint32_t regs_num_64_bit;\n \tuint32_t count = 0;\n \tuint32_t length;\n-\tuint32_t *data;\n \tint ret;\n \n \tret = hns3_get_regs_length(hw, &length, regs->filter);\n \tif (ret)\n \t\treturn ret;\n \n-\tdata = regs->data;\n-\tif (data == NULL) {\n+\tif (regs->data == NULL) {\n \t\tregs->length = length;\n \t\tregs->width = sizeof(uint32_t);\n \t\treturn 0;\n@@ -1335,31 +1526,23 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n \n \t/* fetching per-PF registers values from PF PCIe register space */\n \tcount = hns3_direct_access_regs(hw, regs, count);\n-\tdata += count;\n \n \tif (hns->is_vf)\n \t\treturn 0;\n \n-\tret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);\n-\tif (ret) {\n-\t\thns3_err(hw, \"Get register number failed, ret = %d\", ret);\n-\t\treturn ret;\n-\t}\n-\n-\t/* fetching PF common registers values from firmware */\n-\tret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);\n-\tif (ret) {\n+\tret = hns3_get_32_bit_regs_filtered(hw, regs, &count);\n+\tif (ret != 0) {\n \t\thns3_err(hw, \"Get 32 bit register failed, ret = %d\", ret);\n \t\treturn ret;\n \t}\n-\tdata += regs_num_32_bit;\n \n-\tret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);\n-\tif (ret) {\n+\tret = hns3_get_64_bit_regs_filtered(hw, regs, &count);\n+\tif (ret != 0) {\n \t\thns3_err(hw, \"Get 64 bit register failed, ret = %d\", ret);\n \t\treturn ret;\n \t}\n-\tdata += regs_num_64_bit * HNS3_64_BIT_REG_SIZE;\n \n-\treturn hns3_get_dfx_regs(hw, (void **)&data);\n+\tret = hns3_get_dfx_regs_filtered(hw, regs, &count);\n+\tregs->length = count;\n+\treturn 0;\n }\n", "prefixes": [ "v3", "7/7" ] }