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GET /api/patches/136857/?format=api
{ "id": 136857, "url": "http://patches.dpdk.org/api/patches/136857/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240218051125.717011-2-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240218051125.717011-2-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240218051125.717011-2-igozlan@nvidia.com", "date": "2024-02-18T05:11:16", "name": "[v2,02/10] net/mlx5/hws: add check for not supported fields in VXLAN", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6a684f0b67f6d350292db90cc7ab1806213a495d", "submitter": { "id": 3118, "url": "http://patches.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240218051125.717011-2-igozlan@nvidia.com/mbox/", "series": [ { "id": 31133, "url": "http://patches.dpdk.org/api/series/31133/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31133", "date": "2024-02-18T05:11:16", "name": "[v2,01/10] net/mlx5/hws: skip RTE item when inserting rules by index", "version": 2, "mbox": "http://patches.dpdk.org/series/31133/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136857/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136857/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0B2DB43AFD;\n\tSun, 18 Feb 2024 06:11:52 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9C7894028A;\n\tSun, 18 Feb 2024 06:11:51 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2059.outbound.protection.outlook.com [40.107.237.59])\n by mails.dpdk.org (Postfix) with ESMTP id A954940262\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<igozlan@nvidia.com>, <erezsh@nvidia.com>, <hamdani@nvidia.com>,\n <kliteyn@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Alex Vesker\n <valex@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[v2 02/10] net/mlx5/hws: add check for not supported fields in VXLAN", "Date": "Sun, 18 Feb 2024 07:11:16 +0200", "Message-ID": "<20240218051125.717011-2-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240218051125.717011-1-igozlan@nvidia.com>", "References": "<20240213095038.451299-9-igozlan@nvidia.com>\n <20240218051125.717011-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF00003445:EE_|IA0PR12MB8328:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7b0f8e04-4884-480b-c62d-08dc30401a50", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ZbeByL0wcSmIDY0iBh7NJ+B51LhdlIk32mVReYjEWpnXrPJ+SQyPOtclawoZYpaR0pE5GaOzepHcy7yTFh/jnZCamKbkWOcClbRPf8kQ878wNP9hYk16wUYDHPlu0yj7PEyLpsesorZatZfIf1FR+/BWD93yO4V5O2134ULyM9NlOxWt3MS5cNSNxj2lHpB05L4s2u3oZyVPSNeg8k+9TXWiUa54VWjtn1hMGcoZzRpscRzh9pyNmvmN9xwPkBEOquRKxFBOMD4OqdY/sLmm1ckntzZCbDbnZLdRzERemc7dMX82pftm17Uc5vX9mz3ONi92r8cnjkpWIgU9S2aXGRaAaWZleh5eHVdb8zBrLv/M5J/LVSP3QWIjnCboS6xU2sGI5Lcl4JixNimCayLjOGJTSsNNpk0j0dqY4Yva4rRkf3biWKsI4JmwQj1YfcG351uaT1ovNSN+2ywX+5/vL+bFhyy4vM9rRTHEDfusHqaB5ENEJmCxtcpXPhd6EiSHhZQpgElUKREd1abReArU3sr4y9KXfYssd5mFVTxVOkLFKlh0N7YhI00GGSzbDSwj/3Px9FiAGA40UcYE2uE2lPZhy1xRYJdcUOZ0YvoecHaEkpwcH5xy4g26mnEVoMu5/YbsG+bT3mown/jREaz/6BxZdTRm6i/P1dlZzuWeQgs=", "X-Forefront-Antispam-Report": "CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(376002)(39860400002)(346002)(396003)(230922051799003)(36860700004)(451199024)(1800799012)(82310400011)(64100799003)(186009)(40470700004)(46966006)(82740400003)(86362001)(36756003)(356005)(7636003)(7696005)(316002)(6666004)(6636002)(110136005)(478600001)(6286002)(41300700001)(26005)(336012)(2616005)(426003)(1076003)(921011)(4326008)(8936002)(8676002)(55016003)(70586007)(70206006)(2906002)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Feb 2024 05:11:45.5902 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7b0f8e04-4884-480b-c62d-08dc30401a50", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF00003445.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB8328", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Erez Shitrit <erezsh@nvidia.com>\n\nDon't allow the user to mask over rsvd1 / rsvd2 fields which are not\nsupported.\n\nFixes: dbff89ef806f (\"net/mlx5/hws: fix tunnel protocol checks\")\nSigned-off-by: Erez Shitrit <erezsh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 7 +++++++\n 1 file changed, 7 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 79d98bbf78..8b8757ecac 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -1414,6 +1414,13 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd,\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n+\tif (m && (m->rsvd0[0] != 0 || m->rsvd0[1] != 0 || m->rsvd0[2] != 0 ||\n+\t m->rsvd1 != 0)) {\n+\t\tDR_LOG(ERR, \"reserved fields are not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n \tif (inner) {\n \t\tDR_LOG(ERR, \"Inner VXLAN item not supported\");\n \t\trte_errno = ENOTSUP;\n", "prefixes": [ "v2", "02/10" ] }