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GET /api/patches/136537/?format=api
{ "id": 136537, "url": "http://patches.dpdk.org/api/patches/136537/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240208165038.36265-2-hernan.vargas@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240208165038.36265-2-hernan.vargas@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240208165038.36265-2-hernan.vargas@intel.com", "date": "2024-02-08T16:50:33", "name": "[v7,1/6] doc: fix fpga 5gnr configuration values", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c3e52ed6a50686871a2fbdd2ce2c5d9c9f645cc9", "submitter": { "id": 2659, "url": "http://patches.dpdk.org/api/people/2659/?format=api", "name": "Hernan Vargas", "email": "hernan.vargas@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240208165038.36265-2-hernan.vargas@intel.com/mbox/", "series": [ { "id": 31054, "url": "http://patches.dpdk.org/api/series/31054/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31054", "date": "2024-02-08T16:50:32", "name": "changes for 24.03", "version": 7, "mbox": "http://patches.dpdk.org/series/31054/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136537/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136537/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D0EDE43AE0;\n\tThu, 8 Feb 2024 17:54:03 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BFAD342E13;\n\tThu, 8 Feb 2024 17:53:58 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.13])\n by mails.dpdk.org (Postfix) with ESMTP id CF56140278;\n Thu, 8 Feb 2024 17:53:55 +0100 (CET)", "from fmviesa008.fm.intel.com ([10.60.135.148])\n by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Feb 2024 08:53:54 -0800", "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by fmviesa008.fm.intel.com with ESMTP; 08 Feb 2024 08:53:54 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1707411236; x=1738947236;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=s420qxgENsxnrl2g/vl8+b6q2lMKfU8gv8OKHFeecX0=;\n b=UHrq2NZn/9jE5ob27j20VPi4OW8L4qtx/mGknZPn1oryRe9wztRWuHcg\n uebbz9AVEEsQ1k/b/0IIviXk6azp1Cu0gJ82nKsW/Bgv4Fwyc7SNfP2UZ\n hv9PLmKPqRNBZ7+W9GqoEXqpuCn731pP8OOM+nS87k2tzcvf9xcNuEEtH\n tGC/AYSUOfT6D+rPezjzN7c0EG3FVT5UiN2Xb8if0cs7MP2TUGLnQJazD\n gzJig5huyaUxsVECsQOCir88Bggm8JB9jMNg8Ir6pAHqUQlrIclj+8VqA\n utSFnZWBT3fd+4rQm2WrmESrhESh9Pwp98xVhxoNi6R12FHm7Zvbz8/ZK Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10978\"; a=\"4244293\"", "E=Sophos;i=\"6.05,254,1701158400\";\n d=\"scan'208\";a=\"4244293\"", "E=Sophos;i=\"6.05,254,1701158400\";\n d=\"scan'208\";a=\"1933633\"" ], "X-ExtLoop1": "1", "From": "Hernan Vargas <hernan.vargas@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>, stable@dpdk.org", "Subject": "[PATCH v7 1/6] doc: fix fpga 5gnr configuration values", "Date": "Thu, 8 Feb 2024 08:50:33 -0800", "Message-Id": "<20240208165038.36265-2-hernan.vargas@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20240208165038.36265-1-hernan.vargas@intel.com>", "References": "<20240208165038.36265-1-hernan.vargas@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "flr_timeout was removed from the code a while ago, updating doc.\nFix minor typo in 5GNR example.\n\nFixes: 2d4306438c92 (\"baseband/fpga_5gnr_fec: add configure function\")\nCc: stable@dpdk.org\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n doc/guides/bbdevs/fpga_5gnr_fec.rst | 7 +------\n 1 file changed, 1 insertion(+), 6 deletions(-)", "diff": "diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst\nindex 956dd6bed560..99fc936829a8 100644\n--- a/doc/guides/bbdevs/fpga_5gnr_fec.rst\n+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst\n@@ -100,7 +100,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:\n uint8_t dl_bandwidth;\n uint8_t ul_load_balance;\n uint8_t dl_load_balance;\n- uint16_t flr_time_out;\n };\n \n - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and\n@@ -126,10 +125,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:\n If all hardware queues exceeds the watermark, no code blocks will be\n streamed in from UL/DL code block FIFO.\n \n-- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The\n- time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for\n- the FLR time out then set this setting to 0x262=610.\n-\n \n An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown\n below:\n@@ -154,7 +149,7 @@ below:\n /* setup FPGA PF */\n ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);\n TEST_ASSERT_SUCCESS(ret,\n- \"Failed to configure 4G FPGA PF for bbdev %s\",\n+ \"Failed to configure 5GNR FPGA PF for bbdev %s\",\n info->dev_name);\n \n \n", "prefixes": [ "v7", "1/6" ] }