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GET /api/patches/136488/?format=api
{ "id": 136488, "url": "http://patches.dpdk.org/api/patches/136488/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240207155533.1582031-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240207155533.1582031-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240207155533.1582031-3-michaelba@nvidia.com", "date": "2024-02-07T15:55:28", "name": "[v2,2/7] common/mlx5: reorder modification field PRM list", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "154a93190c25df2290f0afbe339fd364a6014867", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240207155533.1582031-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 31040, "url": "http://patches.dpdk.org/api/series/31040/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31040", "date": "2024-02-07T15:55:26", "name": "net/mlx5: support copy from inner fields", "version": 2, "mbox": "http://patches.dpdk.org/series/31040/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136488/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136488/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC81143AA0;\n\tWed, 7 Feb 2024 16:56:01 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2AB4F42DDB;\n\tWed, 7 Feb 2024 16:56:00 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2055.outbound.protection.outlook.com [40.107.243.55])\n by mails.dpdk.org (Postfix) with ESMTP id A1DB342DD5\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,\n Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v2 2/7] common/mlx5: reorder modification field PRM list", "Date": "Wed, 7 Feb 2024 17:55:28 +0200", "Message-ID": "<20240207155533.1582031-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240207155533.1582031-1-michaelba@nvidia.com>", "References": "<20240206143950.1499532-1-michaelba@nvidia.com>\n <20240207155533.1582031-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF000015CC:EE_|IA1PR12MB7589:EE_", "X-MS-Office365-Filtering-Correlation-Id": "82ba872b-a18e-46fa-0ed5-08dc27f5448d", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n DA/ROrgz0UdRabUtQ7v6On8p+S7l4p51FT//Ars2NsGParAHujdl/a3uiwRmdmmjMuI8cYRO77EAzWJGaCFmvzCrpL9zI6trFSw4tPqGJ/BYWtVn1dci+/AgprhOhYS3lazJPd7wUgPzA/dc0Mahcl4q+xTL5e0GhJlB3T1VLDUDLPuZmggRzhPQvLmCzQDF1B9fBT0LgQBq02uYXRZpzr4TUCbIvbxZXLoWOnm036Q497ZIOGkn+lDAbgTp72++yFPC0MOpTb2PO4IzR/DWqhgiMufdWCC8fhPxmE3jzWalJNbhi0gGV1ziyWx94oOH4F5uFGKXREJIVaAA0KwbKeHZU8jb5AlEtV7h/NMz/0zhwkCqQbVy4nrrp3ENqsFtXulddR9BsBAhIdtAw1uAjjKHYaRspMfcgbM8dc6SQG0IY5CnT+OQz4KAUzGA2KPhakCFlIj99FEzbONObDDK+X1CFJyDkqEN7pXhcyslF8kF2aBMUUgj1S5hMFKHExmDqTKByF8CQM1Wfg1ECW1v9aSkZGwHfQb90yhbVX6+YpfXRNLo5iWMiGSTPfMf/OAmet16x5mgSR5KpqkWsPP81BVW/ffTjUU8mcP7FR2vGS811/FNkxiTY3bom1tTCAyWFQfk+c6eLCrdaQj9E3tnAFNYPGQIaRhxVup119huCaE+2VKtdkT+E+aBNL6HSTdEDJ6SR+6SKGNYeqDpg/Kvgb3iu3ucfc4kCRQIhyFNwYp6nA0X46TVjy+Q7cxlmCq3", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(230922051799003)(186009)(64100799003)(451199024)(1800799012)(82310400011)(46966006)(40470700004)(36840700001)(40480700001)(40460700003)(55016003)(36756003)(478600001)(107886003)(47076005)(7636003)(86362001)(70586007)(2616005)(356005)(426003)(336012)(41300700001)(1076003)(82740400003)(26005)(316002)(83380400001)(6286002)(54906003)(70206006)(6916009)(5660300002)(4326008)(6666004)(8676002)(7696005)(8936002)(36860700001)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Feb 2024 15:55:54.8927 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 82ba872b-a18e-46fa-0ed5-08dc27f5448d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF000015CC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB7589", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Reorder modification field PRM list according to values from lowest to\nhighest.\nThis patch also removes value specification from all fields which their\nvalue is one more than previous one.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 32 ++++++++++++++++----------------\n 1 file changed, 16 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex af16bf4cf6..b758557ef9 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -816,6 +816,7 @@ enum mlx5_modification_field {\n \tMLX5_MODI_OUT_IPV6_HOPLIMIT,\n \tMLX5_MODI_IN_IPV6_HOPLIMIT,\n \tMLX5_MODI_META_DATA_REG_A,\n+\tMLX5_MODI_OUT_IP_PROTOCOL,\n \tMLX5_MODI_META_DATA_REG_B = 0x50,\n \tMLX5_MODI_META_REG_C_0,\n \tMLX5_MODI_META_REG_C_1,\n@@ -829,32 +830,31 @@ enum mlx5_modification_field {\n \tMLX5_MODI_IN_TCP_SEQ_NUM,\n \tMLX5_MODI_OUT_TCP_ACK_NUM,\n \tMLX5_MODI_IN_TCP_ACK_NUM = 0x5C,\n+\tMLX5_MODI_OUT_ESP_SPI = 0x5E,\n \tMLX5_MODI_GTP_TEID = 0x6E,\n \tMLX5_MODI_OUT_IP_ECN = 0x73,\n \tMLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,\n-\tMLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76,\n+\tMLX5_MODI_GTPU_FIRST_EXT_DW_0,\n \tMLX5_MODI_HASH_RESULT = 0x81,\n+\tMLX5_MODI_OUT_ESP_SEQ_NUM,\n \tMLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,\n \tMLX5_MODI_IN_MPLS_LABEL_1,\n \tMLX5_MODI_IN_MPLS_LABEL_2,\n \tMLX5_MODI_IN_MPLS_LABEL_3,\n \tMLX5_MODI_IN_MPLS_LABEL_4,\n-\tMLX5_MODI_OUT_IP_PROTOCOL = 0x4A,\n-\tMLX5_MODI_META_REG_C_8 = 0x8F,\n-\tMLX5_MODI_META_REG_C_9 = 0x90,\n-\tMLX5_MODI_META_REG_C_10 = 0x91,\n-\tMLX5_MODI_META_REG_C_11 = 0x92,\n-\tMLX5_MODI_META_REG_C_12 = 0x93,\n-\tMLX5_MODI_META_REG_C_13 = 0x94,\n-\tMLX5_MODI_META_REG_C_14 = 0x95,\n-\tMLX5_MODI_META_REG_C_15 = 0x96,\n+\tMLX5_MODI_META_REG_C_8,\n+\tMLX5_MODI_META_REG_C_9,\n+\tMLX5_MODI_META_REG_C_10,\n+\tMLX5_MODI_META_REG_C_11,\n+\tMLX5_MODI_META_REG_C_12,\n+\tMLX5_MODI_META_REG_C_13,\n+\tMLX5_MODI_META_REG_C_14,\n+\tMLX5_MODI_META_REG_C_15,\n \tMLX5_MODI_OUT_IPV6_TRAFFIC_CLASS = 0x11C,\n-\tMLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D,\n-\tMLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E,\n-\tMLX5_MODI_OUT_IPV4_IHL = 0x11F,\n-\tMLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120,\n-\tMLX5_MODI_OUT_ESP_SPI = 0x5E,\n-\tMLX5_MODI_OUT_ESP_SEQ_NUM = 0x82,\n+\tMLX5_MODI_OUT_IPV4_TOTAL_LEN,\n+\tMLX5_MODI_OUT_IPV6_PAYLOAD_LEN,\n+\tMLX5_MODI_OUT_IPV4_IHL,\n+\tMLX5_MODI_OUT_TCP_DATA_OFFSET,\n \tMLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126,\n \tMLX5_MODI_INVALID = INT_MAX,\n };\n", "prefixes": [ "v2", "2/7" ] }