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GET /api/patches/136456/?format=api
{ "id": 136456, "url": "http://patches.dpdk.org/api/patches/136456/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240207021849.52988-14-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240207021849.52988-14-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240207021849.52988-14-andrew.boyer@amd.com", "date": "2024-02-07T02:18:49", "name": "[v2,13/13] net/ionic: optimize device start operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5aac0b24de1a774442db1601ec5dff358e504a71", "submitter": { "id": 2861, "url": "http://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240207021849.52988-14-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31030, "url": "http://patches.dpdk.org/api/series/31030/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31030", "date": "2024-02-07T02:18:49", "name": null, "version": 2, "mbox": "http://patches.dpdk.org/series/31030/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136456/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/136456/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 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s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=okDj1gGOQDERFOPPHnEUfrA7tZ9RXZ88UMHOjZEblJg=;\n b=S5cGlRaQzfABt0attxf1IP9CGohrJtW/LrkM5ToNGbAnNHsS7pL/o4StzehlOvdROa6M4XFbzUlITusECAUaKfi1vtuP/4bR2TxnCEKJWKlbw9CywjIChLyUqaLLEkXQJlIA2BkOmKV3ruR7lFwVIANc2unZWjRKBknmRba9Zhg=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH v2 13/13] net/ionic: optimize device start operation", "Date": "Tue, 6 Feb 2024 18:18:49 -0800", "Message-ID": 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xZPx5xa3nvUa5G0m6lFxqFawlu00SXj4hdofeb9zaTmWFAWxd8nbNl5iO+DOczBsNiBEhEm4XotMxOTCFJ/1+9pY/RNMmLEIekmjOEP71RMa6BtVxGCQ0/KaDUo1yvZIgBkQcNF+UNIIejX73tyztgMdnTsOQ0MZVSFRIhrWG2jR1fm9RK6tUvEDE7QeTLd67mNjXQkvUMezu3iJnm8fqv0XCLzC+R8TuCGmWDdsTRdCdC6EI0JzC1w6ME+m9UjWALaBHQ1rhTIzKRRzZoUr+5QgduZ+MChf/ogLD4lni9DsZP6cBgcRsSLJiExwTNl3SQItIUEurbSDAzKcG1exSoWEHdxnmWNuLERFzz1Nz6dGgQEgkeJmwG5ImbkjlcIBcaU7uWhZnfIe4jK8l32NKVVL0SAWDsDiKi1JRxiC00PLwlHT8AXCbucC2H3n66lhgdOPnWRpn5p0RdbhvA7vp9M8HXvhIMs0lY5oQQ+4TGsvoW+bGqypibnFaBYRqOb4gmua6m+ZkRy+jlcq0u2CPdN+w9ONtW6V14IEgnDCMUqiO5eNoiGbiSFbStQ57BW1F6FbzROvgFAmBldLKzzeVLaELOgLR+CG/8RuhGEkd55KCh0eEjMsZe4IX/mJ+DAibdLqAkJKNrtSu+c6pe5j+9KSBT35ajwEqhHhc24mowGFjLPhx5QYCmha71pSlp1Z+Xy2OVIqkopnmDDEUi0Mz1TlLtMSgpej1QmzsTqDzzn0cmDfhEr3RBFHY0aGY5z7kKH98asz5HEO7PIUTbu0bA==", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(230922051799003)(64100799003)(82310400011)(186009)(451199024)(1800799012)(46966006)(40470700004)(36840700001)(36756003)(40460700003)(40480700001)(2616005)(81166007)(83380400001)(47076005)(1076003)(336012)(426003)(82740400003)(41300700001)(16526019)(26005)(356005)(6916009)(6666004)(4326008)(316002)(70586007)(30864003)(70206006)(5660300002)(478600001)(2906002)(86362001)(36860700001)(44832011)(8936002)(8676002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Feb 2024 02:20:00.3068 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 09547da0-50f6-4e5a-8534-08dc2783494e", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF000015CC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5938", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Split the queue_start operation into first-half and second-half helpers.\n\nThis allows us to batch up the queue commands during dev_start(), reducing\nthe outage window when restarting the process by about 1ms per queue.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/net/ionic/ionic_lif.c | 136 +++++++++++++++++++++++----------\n drivers/net/ionic/ionic_lif.h | 6 +-\n drivers/net/ionic/ionic_rxtx.c | 81 ++++++++++++++++----\n drivers/net/ionic/ionic_rxtx.h | 10 +++\n 4 files changed, 176 insertions(+), 57 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex 45317590fa..93a1011772 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -1601,13 +1601,16 @@ ionic_lif_set_features(struct ionic_lif *lif)\n }\n \n int\n-ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n+ionic_lif_txq_init_nowait(struct ionic_tx_qcq *txq)\n {\n \tstruct ionic_qcq *qcq = &txq->qcq;\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_lif *lif = qcq->lif;\n \tstruct ionic_cq *cq = &qcq->cq;\n-\tstruct ionic_admin_ctx ctx = {\n+\tstruct ionic_admin_ctx *ctx = &txq->admin_ctx;\n+\tint err;\n+\n+\t*ctx = (struct ionic_admin_ctx) {\n \t\t.pending_work = true,\n \t\t.cmd.q_init = {\n \t\t\t.opcode = IONIC_CMD_Q_INIT,\n@@ -1621,32 +1624,41 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n \t\t},\n \t};\n-\tint err;\n \n \tif (txq->flags & IONIC_QCQ_F_SG)\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n \tif (txq->flags & IONIC_QCQ_F_CMB) {\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n \t} else {\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n \t}\n \n \tIONIC_PRINT(DEBUG, \"txq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_size %d\",\n-\t\tctx.cmd.q_init.ring_size);\n-\tIONIC_PRINT(DEBUG, \"txq_init.ver %u\", ctx.cmd.q_init.ver);\n+\t\tctx->cmd.q_init.ring_size);\n+\tIONIC_PRINT(DEBUG, \"txq_init.ver %u\", ctx->cmd.q_init.ver);\n \n \tionic_q_reset(q);\n \tionic_cq_reset(cq);\n \n-\terr = ionic_adminq_post_wait(lif, &ctx);\n+\t/* Caller responsible for calling ionic_lif_txq_init_done() */\n+\terr = ionic_adminq_post(lif, ctx);\n \tif (err)\n-\t\treturn err;\n+\t\tctx->pending_work = false;\n+\treturn err;\n+}\n \n-\tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n+void\n+ionic_lif_txq_init_done(struct ionic_tx_qcq *txq)\n+{\n+\tstruct ionic_lif *lif = txq->qcq.lif;\n+\tstruct ionic_queue *q = &txq->qcq.q;\n+\tstruct ionic_admin_ctx *ctx = &txq->admin_ctx;\n+\n+\tq->hw_type = ctx->comp.q_init.hw_type;\n+\tq->hw_index = rte_le_to_cpu_32(ctx->comp.q_init.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \tIONIC_PRINT(DEBUG, \"txq->hw_type %d\", q->hw_type);\n@@ -1654,18 +1666,19 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \tIONIC_PRINT(DEBUG, \"txq->db %p\", q->db);\n \n \ttxq->flags |= IONIC_QCQ_F_INITED;\n-\n-\treturn 0;\n }\n \n int\n-ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n+ionic_lif_rxq_init_nowait(struct ionic_rx_qcq *rxq)\n {\n \tstruct ionic_qcq *qcq = &rxq->qcq;\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_lif *lif = qcq->lif;\n \tstruct ionic_cq *cq = &qcq->cq;\n-\tstruct ionic_admin_ctx ctx = {\n+\tstruct ionic_admin_ctx *ctx = &rxq->admin_ctx;\n+\tint err;\n+\n+\t*ctx = (struct ionic_admin_ctx) {\n \t\t.pending_work = true,\n \t\t.cmd.q_init = {\n \t\t\t.opcode = IONIC_CMD_Q_INIT,\n@@ -1679,32 +1692,41 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n \t\t},\n \t};\n-\tint err;\n \n \tif (rxq->flags & IONIC_QCQ_F_SG)\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n \tif (rxq->flags & IONIC_QCQ_F_CMB) {\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n \t} else {\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n \t}\n \n \tIONIC_PRINT(DEBUG, \"rxq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_size %d\",\n-\t\tctx.cmd.q_init.ring_size);\n-\tIONIC_PRINT(DEBUG, \"rxq_init.ver %u\", ctx.cmd.q_init.ver);\n+\t\tctx->cmd.q_init.ring_size);\n+\tIONIC_PRINT(DEBUG, \"rxq_init.ver %u\", ctx->cmd.q_init.ver);\n \n \tionic_q_reset(q);\n \tionic_cq_reset(cq);\n \n-\terr = ionic_adminq_post_wait(lif, &ctx);\n+\t/* Caller responsible for calling ionic_lif_rxq_init_done() */\n+\terr = ionic_adminq_post(lif, ctx);\n \tif (err)\n-\t\treturn err;\n+\t\tctx->pending_work = false;\n+\treturn err;\n+}\n \n-\tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n+void\n+ionic_lif_rxq_init_done(struct ionic_rx_qcq *rxq)\n+{\n+\tstruct ionic_lif *lif = rxq->qcq.lif;\n+\tstruct ionic_queue *q = &rxq->qcq.q;\n+\tstruct ionic_admin_ctx *ctx = &rxq->admin_ctx;\n+\n+\tq->hw_type = ctx->comp.q_init.hw_type;\n+\tq->hw_index = rte_le_to_cpu_32(ctx->comp.q_init.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \trxq->flags |= IONIC_QCQ_F_INITED;\n@@ -1712,8 +1734,6 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \tIONIC_PRINT(DEBUG, \"rxq->hw_type %d\", q->hw_type);\n \tIONIC_PRINT(DEBUG, \"rxq->hw_index %d\", q->hw_index);\n \tIONIC_PRINT(DEBUG, \"rxq->db %p\", q->db);\n-\n-\treturn 0;\n }\n \n static int\n@@ -1962,9 +1982,11 @@ ionic_lif_configure(struct ionic_lif *lif)\n int\n ionic_lif_start(struct ionic_lif *lif)\n {\n+\tstruct rte_eth_dev *dev = lif->eth_dev;\n \tuint32_t rx_mode;\n-\tuint32_t i;\n+\tuint32_t i, j, chunk;\n \tint err;\n+\tbool fatal = false;\n \n \terr = ionic_lif_rss_setup(lif);\n \tif (err)\n@@ -1985,25 +2007,57 @@ ionic_lif_start(struct ionic_lif *lif)\n \t\t\"on port %u\",\n \t\tlif->nrxqcqs, lif->ntxqcqs, lif->port_id);\n \n-\tfor (i = 0; i < lif->nrxqcqs; i++) {\n-\t\tstruct ionic_rx_qcq *rxq = lif->rxqcqs[i];\n-\t\tif (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {\n-\t\t\terr = ionic_dev_rx_queue_start(lif->eth_dev, i);\n+\tchunk = ionic_adminq_space_avail(lif);\n+\n+\tfor (i = 0; i < lif->nrxqcqs; i += chunk) {\n+\t\tif (lif->rxqcqs[0]->flags & IONIC_QCQ_F_DEFERRED) {\n+\t\t\tIONIC_PRINT(DEBUG, \"Rx queue start deferred\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tfor (j = 0; j < chunk && i + j < lif->nrxqcqs; j++) {\n+\t\t\terr = ionic_dev_rx_queue_start_firsthalf(dev, i + j);\n+\t\t\tif (err) {\n+\t\t\t\tfatal = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \n+\t\tfor (j = 0; j < chunk && i + j < lif->nrxqcqs; j++) {\n+\t\t\t/* Commands that failed to post return immediately */\n+\t\t\terr = ionic_dev_rx_queue_start_secondhalf(dev, i + j);\n \t\t\tif (err)\n-\t\t\t\treturn err;\n+\t\t\t\t/* Don't break */\n+\t\t\t\tfatal = true;\n \t\t}\n \t}\n+\tif (fatal)\n+\t\treturn -EIO;\n \n-\tfor (i = 0; i < lif->ntxqcqs; i++) {\n-\t\tstruct ionic_tx_qcq *txq = lif->txqcqs[i];\n-\t\tif (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {\n-\t\t\terr = ionic_dev_tx_queue_start(lif->eth_dev, i);\n+\tfor (i = 0; i < lif->ntxqcqs; i += chunk) {\n+\t\tif (lif->txqcqs[0]->flags & IONIC_QCQ_F_DEFERRED) {\n+\t\t\tIONIC_PRINT(DEBUG, \"Tx queue start deferred\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tfor (j = 0; j < chunk && i + j < lif->ntxqcqs; j++) {\n+\t\t\terr = ionic_dev_tx_queue_start_firsthalf(dev, i + j);\n+\t\t\tif (err) {\n+\t\t\t\tfatal = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \n+\t\tfor (j = 0; j < chunk && i + j < lif->ntxqcqs; j++) {\n+\t\t\t/* Commands that failed to post return immediately */\n+\t\t\terr = ionic_dev_tx_queue_start_secondhalf(dev, i + j);\n \t\t\tif (err)\n-\t\t\t\treturn err;\n+\t\t\t\t/* Don't break */\n+\t\t\t\tfatal = true;\n \t\t}\n \t}\n+\tif (fatal)\n+\t\treturn -EIO;\n \n \t/* Carrier ON here */\n \tlif->state |= IONIC_LIF_F_UP;\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex ee13f5b7c8..591cf1a2ff 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -228,11 +228,13 @@ int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id,\n \tstruct ionic_tx_qcq **qcq_out);\n void ionic_qcq_free(struct ionic_qcq *qcq);\n \n-int ionic_lif_rxq_init(struct ionic_rx_qcq *rxq);\n+int ionic_lif_rxq_init_nowait(struct ionic_rx_qcq *rxq);\n+void ionic_lif_rxq_init_done(struct ionic_rx_qcq *rxq);\n void ionic_lif_rxq_deinit_nowait(struct ionic_rx_qcq *rxq);\n void ionic_lif_rxq_stats(struct ionic_rx_qcq *rxq);\n \n-int ionic_lif_txq_init(struct ionic_tx_qcq *txq);\n+int ionic_lif_txq_init_nowait(struct ionic_tx_qcq *txq);\n+void ionic_lif_txq_init_done(struct ionic_tx_qcq *txq);\n void ionic_lif_txq_deinit_nowait(struct ionic_tx_qcq *txq);\n void ionic_lif_txq_stats(struct ionic_tx_qcq *txq);\n \ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex 774dc596c0..ad04e987eb 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -203,27 +203,54 @@ ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,\n * Start Transmit Units for specified queue.\n */\n int __rte_cold\n-ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)\n+ionic_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n {\n-\tuint8_t *tx_queue_state = eth_dev->data->tx_queue_state;\n-\tstruct ionic_tx_qcq *txq;\n \tint err;\n \n+\terr = ionic_dev_tx_queue_start_firsthalf(dev, tx_queue_id);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn ionic_dev_tx_queue_start_secondhalf(dev, tx_queue_id);\n+}\n+\n+int __rte_cold\n+ionic_dev_tx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t tx_queue_id)\n+{\n+\tuint8_t *tx_queue_state = dev->data->tx_queue_state;\n+\tstruct ionic_tx_qcq *txq = dev->data->tx_queues[tx_queue_id];\n+\n \tif (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {\n \t\tIONIC_PRINT(DEBUG, \"TX queue %u already started\",\n \t\t\ttx_queue_id);\n \t\treturn 0;\n \t}\n \n-\ttxq = eth_dev->data->tx_queues[tx_queue_id];\n-\n \tIONIC_PRINT(DEBUG, \"Starting TX queue %u, %u descs\",\n \t\ttx_queue_id, txq->qcq.q.num_descs);\n \n-\terr = ionic_lif_txq_init(txq);\n+\treturn ionic_lif_txq_init_nowait(txq);\n+}\n+\n+int __rte_cold\n+ionic_dev_tx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t tx_queue_id)\n+{\n+\tuint8_t *tx_queue_state = dev->data->tx_queue_state;\n+\tstruct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(dev);\n+\tstruct ionic_tx_qcq *txq = dev->data->tx_queues[tx_queue_id];\n+\tint err;\n+\n+\tif (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED)\n+\t\treturn 0;\n+\n+\terr = ionic_adminq_wait(lif, &txq->admin_ctx);\n \tif (err)\n \t\treturn err;\n \n+\tionic_lif_txq_init_done(txq);\n+\n \ttx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n \treturn 0;\n@@ -680,22 +707,31 @@ ionic_rx_init_descriptors(struct ionic_rx_qcq *rxq)\n * Start Receive Units for specified queue.\n */\n int __rte_cold\n-ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n+ionic_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n-\tuint8_t *rx_queue_state = eth_dev->data->rx_queue_state;\n-\tstruct ionic_rx_qcq *rxq;\n-\tstruct ionic_queue *q;\n \tint err;\n \n+\terr = ionic_dev_rx_queue_start_firsthalf(dev, rx_queue_id);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn ionic_dev_rx_queue_start_secondhalf(dev, rx_queue_id);\n+}\n+\n+int __rte_cold\n+ionic_dev_rx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t rx_queue_id)\n+{\n+\tuint8_t *rx_queue_state = dev->data->rx_queue_state;\n+\tstruct ionic_rx_qcq *rxq = dev->data->rx_queues[rx_queue_id];\n+\tstruct ionic_queue *q = &rxq->qcq.q;\n+\n \tif (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {\n \t\tIONIC_PRINT(DEBUG, \"RX queue %u already started\",\n \t\t\trx_queue_id);\n \t\treturn 0;\n \t}\n \n-\trxq = eth_dev->data->rx_queues[rx_queue_id];\n-\tq = &rxq->qcq.q;\n-\n \trxq->frame_size = rxq->qcq.lif->frame_size - RTE_ETHER_CRC_LEN;\n \n \t/* Recalculate segment count based on MTU */\n@@ -707,10 +743,27 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \n \tionic_rx_init_descriptors(rxq);\n \n-\terr = ionic_lif_rxq_init(rxq);\n+\treturn ionic_lif_rxq_init_nowait(rxq);\n+}\n+\n+int __rte_cold\n+ionic_dev_rx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t rx_queue_id)\n+{\n+\tuint8_t *rx_queue_state = dev->data->rx_queue_state;\n+\tstruct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(dev);\n+\tstruct ionic_rx_qcq *rxq = dev->data->rx_queues[rx_queue_id];\n+\tint err;\n+\n+\tif (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED)\n+\t\treturn 0;\n+\n+\terr = ionic_adminq_wait(lif, &rxq->admin_ctx);\n \tif (err)\n \t\treturn err;\n \n+\tionic_lif_rxq_init_done(rxq);\n+\n \t/* Allocate buffers for descriptor ring */\n \tif (rxq->flags & IONIC_QCQ_F_SG)\n \t\terr = ionic_rx_fill_sg(rxq);\ndiff --git a/drivers/net/ionic/ionic_rxtx.h b/drivers/net/ionic/ionic_rxtx.h\nindex 7ca23178cc..a342afec54 100644\n--- a/drivers/net/ionic/ionic_rxtx.h\n+++ b/drivers/net/ionic/ionic_rxtx.h\n@@ -46,6 +46,16 @@ void ionic_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n int ionic_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n int ionic_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n \n+/* Helpers for optimized dev_start() */\n+int ionic_dev_rx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\tuint16_t rx_queue_id);\n+int ionic_dev_rx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\tuint16_t rx_queue_id);\n+int ionic_dev_tx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\tuint16_t tx_queue_id);\n+int ionic_dev_tx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\tuint16_t tx_queue_id);\n+\n /* Helpers for optimized dev_stop() */\n void ionic_dev_rx_queue_stop_firsthalf(struct rte_eth_dev *dev,\n \tuint16_t rx_queue_id);\n", "prefixes": [ "v2", "13/13" ] }