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GET /api/patches/136431/?format=api
{ "id": 136431, "url": "http://patches.dpdk.org/api/patches/136431/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240206143950.1499532-7-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240206143950.1499532-7-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240206143950.1499532-7-michaelba@nvidia.com", "date": "2024-02-06T14:39:49", "name": "[v1,6/7] net/mlx5: support modify IPv6 traffic class field", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9ba1d754b834bd01fcd0f551dfeac3e8db0caa36", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240206143950.1499532-7-michaelba@nvidia.com/mbox/", "series": [ { "id": 31011, "url": "http://patches.dpdk.org/api/series/31011/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31011", "date": "2024-02-06T14:39:45", "name": "net/mlx5: support copy from inner fields", "version": 1, "mbox": "http://patches.dpdk.org/series/31011/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136431/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136431/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AB2C443A3A;\n\tTue, 6 Feb 2024 15:41:00 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 614D842D55;\n\tTue, 6 Feb 2024 15:40:31 +0100 (CET)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2054.outbound.protection.outlook.com [40.107.223.54])\n by mails.dpdk.org (Postfix) with ESMTP id BBB2C42D2E\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,\n Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v1 6/7] net/mlx5: support modify IPv6 traffic class field", "Date": "Tue, 6 Feb 2024 16:39:49 +0200", "Message-ID": "<20240206143950.1499532-7-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240206143950.1499532-1-michaelba@nvidia.com>", "References": "<20240206143950.1499532-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF0000343B:EE_|DM8PR12MB5494:EE_", "X-MS-Office365-Filtering-Correlation-Id": "bb18fe2e-1bb7-4d39-4141-08dc27218e06", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n TO+sx1t0mX0Nrkyl6Q1+JMrNw5M2HSK+T4/n/poMv4ZjYuXc3LkDeSCHb1iKpZIDPdsciIjlZW4BNN3ArrOtXx99x4i+rPFcZgfSGnj4kODQo9oglN1eEup+G/GwHphg6Cx5gOsN1WEMa7SwEoPSCYH/3POXSG5qqIzQKaJQ7fI4v7mXuzLMa54IVkNLEj0nIaxIeiv9f3q5WkQVcx5oM8apkpAkl5oNfQDzhZUux86/rvQbjM6pFyEiIsw7OangAZn20DPErndHfKPIxAwk1TogjN7X9Sd5t7SFQoWVlisXnV5LWmi7MM5NUX8tl4rQHsFVVCLazhtsIS8sD/HKTeRB4WlNCzavtzJVTnfSwtaP7nCqFWYVOF+PsPEmvvcbnORW5hM5i+deSNubCYtCxupS44iHYKpMWC6SvUMTvaDMH72ks6NBAZrVOwv5pmMlC3NufzzTKDHgZ5CjKLqx6fyG1WIMrQ5gwOsctx/iSehT3+vpbnc/kz7vAa+tirmhXr1cUdM/eXSzbgjNPN/WjfwqNCWhbdNeqJTwSzsGRuwubV/tk7p4HJsCxuUW5OOgMl7SI0kRjP685k9OLy/Hd3va8sRwWO/X5IHoYt9tpRWzK2iVA7KBdJgQqtPwVzdnQzZ1tNNB8BaKiy24IS5lqeAKOg+e0l1hI+LwmADjzbX/9ro4PAeURFS5EnzLSS0VYEqx5gnd8UkwUQl6mx7VTU1CglUfhHzsZXcGgukdh4oqEkX4IEHsRPIbxcFNiCiK", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(346002)(376002)(136003)(39860400002)(230922051799003)(1800799012)(82310400011)(64100799003)(451199024)(186009)(40470700004)(46966006)(36840700001)(40480700001)(55016003)(36756003)(40460700003)(478600001)(7636003)(1076003)(107886003)(83380400001)(336012)(41300700001)(356005)(426003)(82740400003)(6286002)(47076005)(26005)(2616005)(70206006)(7696005)(6916009)(2906002)(4326008)(5660300002)(86362001)(54906003)(70586007)(8936002)(6666004)(8676002)(316002)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Feb 2024 14:40:24.8383 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bb18fe2e-1bb7-4d39-4141-08dc27218e06", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF0000343B.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM8PR12MB5494", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add HW steering support for IPv6 traffic class field modification.\nCopy from inner IPv6 traffic class field is also supported using\n\"level=2\".\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/rel_notes/release_24_03.rst | 1 +\n drivers/net/mlx5/mlx5_flow_dv.c | 11 +++++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 3 ++-\n 3 files changed, 14 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 10268b7879..272bc9d056 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -100,6 +100,7 @@ New Features\n * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SPI`` flow action.\n * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SEQ_NUM`` flow action.\n * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_PROTO`` flow action.\n+ * Added HW steering support for modify field ``RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS`` flow action.\n \n \n Removed Items\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 8454d00d4f..90ef21d75b 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1394,6 +1394,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev,\n \t\treturn 32;\n \tcase RTE_FLOW_FIELD_IPV6_DSCP:\n \t\treturn 6;\n+\tcase RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:\n \tcase RTE_FLOW_FIELD_IPV6_HOPLIMIT:\n \tcase RTE_FLOW_FIELD_IPV6_PROTO:\n \t\treturn 8;\n@@ -1795,6 +1796,16 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:\n+\t\tMLX5_ASSERT(data->offset + width <= 8);\n+\t\toff_be = 8 - (data->offset + width);\n+\t\tmodi_id = CALC_MODI_ID(IPV6_TRAFFIC_CLASS, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex fc0f9dabb3..90e3cf2555 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2871,7 +2871,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n \t\t * bits left. Shift the data left for IPV6 DSCP\n \t\t */\n \t\tif (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&\n-\t\t !(mask & MLX5_IPV6_HDR_ECN_MASK))\n+\t\t mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)\n \t\t\tdata <<= MLX5_IPV6_HDR_DSCP_SHIFT;\n \t\tdata = (data & mask) >> off_b;\n \t\tjob->mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);\n@@ -5058,6 +5058,7 @@ flow_hw_validate_modify_field_level(const struct rte_flow_action_modify_data *da\n \tcase RTE_FLOW_FIELD_IPV4_TTL:\n \tcase RTE_FLOW_FIELD_IPV4_SRC:\n \tcase RTE_FLOW_FIELD_IPV4_DST:\n+\tcase RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:\n \tcase RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:\n \tcase RTE_FLOW_FIELD_IPV6_HOPLIMIT:\n \tcase RTE_FLOW_FIELD_IPV6_SRC:\n", "prefixes": [ "v1", "6/7" ] }