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GET /api/patches/136151/?format=api
{ "id": 136151, "url": "http://patches.dpdk.org/api/patches/136151/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240125133043.575860-9-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240125133043.575860-9-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240125133043.575860-9-michaelba@nvidia.com", "date": "2024-01-25T13:30:28", "name": "[v2,08/23] common/mlx5: add PRM attribute for TLV sample", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6468c5a1bb9f8bf3911c4d60e3ea27c0c4badb4c", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240125133043.575860-9-michaelba@nvidia.com/mbox/", "series": [ { "id": 30916, "url": "http://patches.dpdk.org/api/series/30916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30916", "date": "2024-01-25T13:30:20", "name": "net/mlx5: support Geneve and options for HWS", "version": 2, "mbox": "http://patches.dpdk.org/series/30916/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136151/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136151/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4C73A439C1;\n\tThu, 25 Jan 2024 14:32:15 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2F2E142E3F;\n\tThu, 25 Jan 2024 14:31:25 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2059.outbound.protection.outlook.com [40.107.237.59])\n by mails.dpdk.org (Postfix) with ESMTP id 7C50242E44\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v2 08/23] common/mlx5: add PRM attribute for TLV sample", "Date": "Thu, 25 Jan 2024 15:30:28 +0200", "Message-ID": "<20240125133043.575860-9-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240125133043.575860-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>\n <20240125133043.575860-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3E:EE_|SJ0PR12MB6710:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a7ff877e-d004-447f-b03c-08dc1da9eac1", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n y5POk7vF62jL/uFcHqQwYa/dbjK4K1KmfekqUbKPy+SVYfryLutg0KXhURNWtSU5MCeNxJOEjRrKfZA9t/iPtIOoPnGelk8is5Ox+NCSdORv58hnKQkYB5G9KTsZVQudrigQ5yhnS0btQ49GN/SonNhakY8XQQqmumMeJGQMrA3YXq53TG3J4n5hCIGNURBcx4qaolCzd/PKPkPyLdbPPevehV5b/x6l1/XqY9k3kPsv8iUkIY3DSUd3UfcTSQiM/c8hAxo83qsSfG8JCgVm4fdhQAWLbHnSrMK45svDqRDpln4pFSFE4E4ZJtR1OrpM82XZYVx/CS5eHoZsM/NSsUfCI+RTLo6tKji/cEiIcO38peGqPyzo3NVxxNvbjQnwVwNqSPJBA6srkwRnq/pKJ8eQqf0P2hD9iKpsdBHnaN1/iQ6Z60d+GjRvME4g2Hi8VWkXgDiGJ4xojM2QPs9eRIJmdRPA/xbYw2BBjfpfcjkFHT7DMznhjAwvzcmXz2oc0mwYiEre0XHQf8BVa6EZQD7b9hCzeO6TN1955UsWDq59rESDienJ9JNephwUMipIbAzDPwmTNXZUVNeRCLw1gJG+B812A+bpgYuN3kaJPNlX/YsfjR6V1hxgSR6wGob4E9Nahuhqb5ZK+cMOjaR90daOtOM+2QbsiH9Wg+EpuZqQYw40eQNr2h868UdK1neozqUQOkJPWCSd9/h0tdjMwMa7dOMcKK7yl+4WEjUM7ZjROHmD6BVgvzWOYAft5M9X", "X-Forefront-Antispam-Report": "CIP:216.228.118.232; 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Ip=[216.228.118.232];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3E.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB6710", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add GENEVE TLV sample fields in 2 places:\n1. New HCA capabilities indicating GENEVE TLV sample is supported.\n2. New fields in \"mlx5_ifc_geneve_tlv_option_bits\" structure.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 18 ++++++++++++++++--\n drivers/common/mlx5/mlx5_devx_cmds.h | 9 +++++++--\n drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++----\n 3 files changed, 34 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex c783fc0e10..68137dc535 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -968,6 +968,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\tmax_geneve_tlv_options);\n \tattr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\tmax_geneve_tlv_option_data_len);\n+\tattr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t geneve_tlv_option_offset);\n+\tattr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t geneve_tlv_sample);\n \tattr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t query_match_sample_info);\n \tattr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);\n@@ -2886,11 +2890,21 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n \t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n \tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n \t\t MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);\n-\tMLX5_SET(geneve_tlv_option, opt, option_class,\n-\t\t rte_be_to_cpu_16(attr->option_class));\n \tMLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);\n \tMLX5_SET(geneve_tlv_option, opt, option_data_length,\n \t\t attr->option_data_len);\n+\tif (attr->option_class_ignore)\n+\t\tMLX5_SET(geneve_tlv_option, opt, option_class_ignore,\n+\t\t\t attr->option_class_ignore);\n+\telse\n+\t\tMLX5_SET(geneve_tlv_option, opt, option_class,\n+\t\t\t rte_be_to_cpu_16(attr->option_class));\n+\tif (attr->offset_valid) {\n+\t\tMLX5_SET(geneve_tlv_option, opt, sample_offset_valid,\n+\t\t\t attr->offset_valid);\n+\t\tMLX5_SET(geneve_tlv_option, opt, sample_offset,\n+\t\t\t attr->sample_offset);\n+\t}\n \tgeneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,\n \t\t\t\t\t\t\t sizeof(in), out,\n \t\t\t\t\t\t\t sizeof(out));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex d11f1d650f..4f264560a9 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -212,8 +212,10 @@ struct mlx5_hca_attr {\n \tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n \tuint16_t lro_min_mss_size;\n \tuint32_t flex_parser_protocols;\n-\tuint32_t max_geneve_tlv_options;\n-\tuint32_t max_geneve_tlv_option_data_len;\n+\tuint32_t max_geneve_tlv_options:8;\n+\tuint32_t max_geneve_tlv_option_data_len:5;\n+\tuint32_t geneve_tlv_sample:1;\n+\tuint32_t geneve_tlv_option_offset:1;\n \tuint32_t hairpin:1;\n \tuint32_t log_max_hairpin_queues:5;\n \tuint32_t log_max_hairpin_wq_data_sz:5;\n@@ -675,6 +677,9 @@ struct mlx5_devx_geneve_tlv_option_attr {\n \tuint32_t option_class:16;\n \tuint32_t option_type:8;\n \tuint32_t option_data_len:5;\n+\tuint32_t option_class_ignore:1;\n+\tuint32_t offset_valid:1;\n+\tuint32_t sample_offset:8;\n };\n \n /* mlx5_devx_cmds.c */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 69404b5ed8..f15e3c2bd7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1854,7 +1854,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 num_of_uars_per_page[0x20];\n \tu8 flex_parser_protocols[0x20];\n \tu8 max_geneve_tlv_options[0x8];\n-\tu8 reserved_at_568[0x3];\n+\tu8 geneve_tlv_sample[0x1];\n+\tu8 geneve_tlv_option_offset[0x1];\n+\tu8 reserved_at_56a[0x1];\n \tu8 max_geneve_tlv_option_data_len[0x5];\n \tu8 flex_parser_header_modify[0x1];\n \tu8 reserved_at_571[0x2];\n@@ -3424,16 +3426,21 @@ struct mlx5_ifc_virtio_q_counters_bits {\n \n struct mlx5_ifc_geneve_tlv_option_bits {\n \tu8 modify_field_select[0x40];\n-\tu8 reserved_at_40[0x18];\n+\tu8 reserved_at_40[0x8];\n+\tu8 sample_offset[0x8];\n+\tu8 sample_id_valid[0x1];\n+\tu8 sample_offset_valid[0x1];\n+\tu8 option_class_ignore[0x1];\n+\tu8 reserved_at_53[0x5];\n \tu8 geneve_option_fte_index[0x8];\n \tu8 option_class[0x10];\n \tu8 option_type[0x8];\n \tu8 reserved_at_78[0x3];\n \tu8 option_data_length[0x5];\n-\tu8 reserved_at_80[0x180];\n+\tu8 geneve_sample_field_id[0x20];\n+\tu8 reserved_at_a0[0x160];\n };\n \n-\n enum mlx5_ifc_rtc_update_mode {\n \tMLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0,\n \tMLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1,\n", "prefixes": [ "v2", "08/23" ] }