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{ "id": 136147, "url": "http://patches.dpdk.org/api/patches/136147/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240125133043.575860-6-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240125133043.575860-6-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240125133043.575860-6-michaelba@nvidia.com", "date": "2024-01-25T13:30:25", "name": "[v2,05/23] net/mlx5: fix GENEVE option item translation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e2e90be077841355ba2a576a7400d44b2fbfc4da", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240125133043.575860-6-michaelba@nvidia.com/mbox/", "series": [ { "id": 30916, "url": "http://patches.dpdk.org/api/series/30916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30916", "date": "2024-01-25T13:30:20", "name": "net/mlx5: support Geneve and options for HWS", "version": 2, "mbox": "http://patches.dpdk.org/series/30916/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136147/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136147/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3624A439C1;\n\tThu, 25 Jan 2024 14:31:39 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EEC7942E32;\n\tThu, 25 Jan 2024 14:31:14 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2055.outbound.protection.outlook.com [40.107.237.55])\n by mails.dpdk.org (Postfix) with ESMTP id 00CE442E25\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v2 05/23] net/mlx5: fix GENEVE option item translation", "Date": "Thu, 25 Jan 2024 15:30:25 +0200", "Message-ID": "<20240125133043.575860-6-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240125133043.575860-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>\n <20240125133043.575860-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD4:EE_|CYYPR12MB8702:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7acb1136-2d06-441f-59ad-08dc1da9e592", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n wFX62L829vdEmdXwaokn5wBJqOqNx/xdZ9hlbIBqpv4jZHqczZAkWhSGivSG5OFwIcEWmyHN3RluhB8vGrx3bF3Ez7DmfIab9F3GJHQazRb26emyEHxPsWF/6vNFoK5BuUKlfQ+uQ7KuRxgfvG6HBGIBP2Mnu0JKw6mLT8Qd3cYjLm9yMyy12lnmq/WuSWmXx1GkkBcagh8LoUQdGblQZjjCnaHwWs9P/9FkFZYaAVLLrswczsE1RgmLPTWsoZHK8FC9KIhWSYH02ctBqL3uzmlcQMKJWnB3vMDshpm4WSvVlVzmbXm9aPHqEkDb3KNvni93hY40EbBFpXiGBKommNyJ12V1VBATmTtukefMO+OTrp6D1kcQ7UjgujMcgTXJxtK6GdaSl0ilGOUy1wSoxxHIrCWyykvi6QbMY/CICYfbPDFWthpM1yFQlyo98+zlfw1loVT87pGV7FaA7EDFM2m8n3aQYmZCujvjAUxPXYxLMeLdX3SVIBs0LABglWx2FeafDqzILX8DwmQOFyvHr7MkvpKOuZ6lW9iHU7PG2JtgQjWUnPCVs9B4Yf9922sx5UovRhckgvn2bYbXBURUAyrv6o3+F8c7e7JCKaXUtpTz/kK8aZrun/1qkoFksMmbLyjq2+rYFKVOSJ9uhrJn3DenFPJl49yvOXFhR2p09GKV7c6aoEKHHHQyKqnib4CkmqLfAuZ7lWsL499U+ERhU4q5jtbLXx/VLZrVB4QiPs5G8/jEvN+aQDs+asK/7/6J", "X-Forefront-Antispam-Report": "CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(376002)(39860400002)(346002)(396003)(136003)(230922051799003)(64100799003)(1800799012)(186009)(451199024)(82310400011)(40470700004)(46966006)(36840700001)(36860700001)(5660300002)(2906002)(4326008)(8676002)(6916009)(316002)(54906003)(86362001)(70206006)(8936002)(70586007)(36756003)(47076005)(82740400003)(356005)(7636003)(6666004)(83380400001)(7696005)(2616005)(26005)(478600001)(426003)(336012)(41300700001)(40480700001)(107886003)(1076003)(40460700003)(6286002)(55016003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Jan 2024 13:31:11.7082 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7acb1136-2d06-441f-59ad-08dc1da9e592", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD4.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CYYPR12MB8702", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The \"flow_dv_translate_item_geneve_opt()\" function is called twice per\nflow rule, for either matcher focusing the mask or value focusing the\nspec.\nThe spec is always provided and its field \"option_len\" indicates the\ndata size for both spec and mask. For using it, function has another\npointer \"geneve_opt_vv\" representing the spec regardless to focusing\nwhile the \"geneve_opt_v\" pointer represents the mask for matcher and\nspec for rule creation.\n\nThe current implementation has 2 issues:\n1. geneve_opt_v get the spec in rule creation as sane as geneve_opt_vv,\n but function use if-else which is bacicly has same value.\n2. function uses \"option_len\" from \"geneve_opt_v\" instead of\n \"geneve_opt_v\" even when the focus is on mask, for HWS the mask value\n may be 0 even data is valid.\n\nThis patch refactors the function implementation to avoid those issues.\n\nFixes: cd4ab742064a (\"net/mlx5: split flow item matcher and value translation\")\nCc: suanmingm@nvidia.com\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 28 +++++++++++-----------------\n 1 file changed, 11 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex b091eb9d11..cc5549f9ce 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -10103,13 +10103,13 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key,\n {\n \tconst struct rte_flow_item_geneve_opt *geneve_opt_m;\n \tconst struct rte_flow_item_geneve_opt *geneve_opt_v;\n-\tconst struct rte_flow_item_geneve_opt *geneve_opt_vv = item->spec;\n+\tconst struct rte_flow_item_geneve_opt *orig_spec = item->spec;\n \tvoid *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);\n \trte_be32_t opt_data_key = 0, opt_data_mask = 0;\n-\tuint32_t *data;\n+\tsize_t option_byte_len;\n \tint ret = 0;\n \n-\tif (MLX5_ITEM_VALID(item, key_type))\n+\tif (MLX5_ITEM_VALID(item, key_type) || !orig_spec)\n \t\treturn -1;\n \tMLX5_ITEM_UPDATE(item, key_type, geneve_opt_v, geneve_opt_m,\n \t\t\t &rte_flow_item_geneve_opt_mask);\n@@ -10122,21 +10122,15 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key,\n \t\t\treturn ret;\n \t\t}\n \t}\n-\t/* Set the data. */\n-\tif (key_type == MLX5_SET_MATCHER_SW_V)\n-\t\tdata = geneve_opt_vv->data;\n-\telse\n-\t\tdata = geneve_opt_v->data;\n-\tif (data) {\n-\t\tmemcpy(&opt_data_key, data,\n-\t\t\tRTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),\n-\t\t\t\tsizeof(opt_data_key)));\n-\t\tmemcpy(&opt_data_mask, geneve_opt_m->data,\n-\t\t\tRTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),\n-\t\t\t\tsizeof(opt_data_mask)));\n+\t/* Convert the option length from DW to bytes for using memcpy. */\n+\toption_byte_len = RTE_MIN((size_t)(orig_spec->option_len * 4),\n+\t\t\t\t sizeof(rte_be32_t));\n+\tif (geneve_opt_v->data) {\n+\t\tmemcpy(&opt_data_key, geneve_opt_v->data, option_byte_len);\n+\t\tmemcpy(&opt_data_mask, geneve_opt_m->data, option_byte_len);\n \t\tMLX5_SET(fte_match_set_misc3, misc3_v,\n-\t\t\t\tgeneve_tlv_option_0_data,\n-\t\t\trte_be_to_cpu_32(opt_data_key & opt_data_mask));\n+\t\t\t geneve_tlv_option_0_data,\n+\t\t\t rte_be_to_cpu_32(opt_data_key & opt_data_mask));\n \t}\n \treturn ret;\n }\n", "prefixes": [ "v2", "05/23" ] }