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GET /api/patches/135874/?format=api
{ "id": 135874, "url": "http://patches.dpdk.org/api/patches/135874/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240115091318.1053433-4-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240115091318.1053433-4-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240115091318.1053433-4-suanmingm@nvidia.com", "date": "2024-01-15T09:13:18", "name": "[v3,3/3] net/mlx5: add compare item support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "83cfb9c04351eb6b26ac55e8e7753e3603922d5d", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240115091318.1053433-4-suanmingm@nvidia.com/mbox/", "series": [ { "id": 30800, "url": "http://patches.dpdk.org/api/series/30800/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30800", "date": "2024-01-15T09:13:15", "name": "ethdev: add RTE_FLOW_ITEM_TYPE_COMPARE", "version": 3, "mbox": "http://patches.dpdk.org/series/30800/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135874/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135874/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 37C16438CD;\n\tMon, 15 Jan 2024 10:14:07 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4389040649;\n\tMon, 15 Jan 2024 10:14:06 +0100 (CET)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam02on2087.outbound.protection.outlook.com [40.107.212.87])\n by mails.dpdk.org (Postfix) with ESMTP id CAA3240647\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<orika@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, \"Viacheslav\n Ovsiienko\" <viacheslavo@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 3/3] net/mlx5: add compare item support", "Date": "Mon, 15 Jan 2024 17:13:18 +0800", "Message-ID": "<20240115091318.1053433-4-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240115091318.1053433-1-suanmingm@nvidia.com>", "References": "<20231219013337.531548-1-suanmingm@nvidia.com>\n <20240115091318.1053433-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ1PEPF00001CE5:EE_|DM4PR12MB5890:EE_", "X-MS-Office365-Filtering-Correlation-Id": "62a7e266-8e71-46e4-5831-08dc15aa50a2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n m3qpAEpu4Jqi8NTTBX67t3yY7EumXNDll6suDMVXjwEv5jjW+SoqFBTmVW4RI7N/zOw1DRhuIkpyhqqmTYLopgqGbS2REbln0WcetJ2OF2QB5Z6R7njwejWJKaQsktUlBF+ihLYRuVV9hVeqlxtPI3SOlbESch4Imz6tUl4x6/sEtliPn8oBOuLGyKfAgixEx+HB9Bt9WB70kqJwvBo/85gZlI51ftRtAjfiLaeIBHOr0a/ZeUy1l+pz3Qx64RimKt51WgtmcqcdZ8iUxoafv9mtDfYeCm3wamn0L05qEfPLmPOa3Nx/6HQCioqrtW5tUa/92IIsk2oVC8/Np10Pv490mUQtyhVdevmJSt+k7q9GBW1lGw5a9BCP7caxR/eTBiY7+1Mkiw9qZ6dzLEqiGFxzEARRM53Shk6PdrosUT4ZiI48/s9Kq0jehjbpc7TnqAzCT3XxxxUpmNW7AAdEXnoXE6VSteT5LFeQRkC3OC96bVeZDnxV/jcgNucRPaPo6gc3tXLPewjeyJjU/Vp/LDDQmB5nwyOR6HGFwlNptdyOpk8YLng2tV9v7eEalE9L+KQ9Srx+xjgpT6e1IuW4d/GVFWy/9bNgZhho/5Fxlj5JeHmtoj4vE10y3k7m+F0f5Z5Uud576UABh9XVgOaZ1ulWyCNLeo42PB35gqe83EWM3yDqfx7B3n0EyBRrIt3EcoQspxmce1dFBdrv38iKtK5LsvoZ2ObLmSJydhyMc9ux7EHER8I0sV2CI1Tj7Ypo", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SJ1PEPF00001CE5.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5890", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The compare item allows adding flow match with comparison\nresult. This commit adds compare item support to the PMD\ncode.\n\nDue to HW limitation:\n - Only HWS supported.\n - Only 32-bit comparison is supported.\n - Only single compare flow is supported in the flow table.\n - Only match with compare result between packet fields is\n supported.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 7 +++\n doc/guides/rel_notes/release_24_03.rst | 2 +-\n drivers/net/mlx5/mlx5_flow.h | 3 ++\n drivers/net/mlx5/mlx5_flow_hw.c | 73 ++++++++++++++++++++++++++\n 5 files changed, 85 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex 0739fe9d63..00e9348fc6 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -56,6 +56,7 @@ Usage doc = Y\n \n [rte_flow items]\n aggr_affinity = Y\n+compare = Y\n conntrack = Y\n ecpri = Y\n esp = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 7bfd6c6aeb..1bb7d0665d 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -780,6 +780,13 @@ Limitations\n The flow engine of a process cannot move from active to standby mode\n if preceding active application rules are still present and vice versa.\n \n+- Match with compare result item (``RTE_FLOW_ITEM_TYPE_COMPARE``):\n+\n+ - Only supported in HW steering(``dv_flow_en`` = 2) mode.\n+ - Only single flow is supported to the flow table.\n+ - Only 32-bit comparison is supported.\n+ - Only match with compare result between packet fields is supported.\n+\n \n Statistics\n ----------\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 8c8c661218..ef9c5d55a1 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -63,7 +63,7 @@ New Features\n * **Updated NVIDIA mlx5 driver.**\n \n * Added support for accumulating from src field to dst field.\n-\n+ * Added support for comparing result between packet fields or value.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 8e2034473c..6698de2a3e 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -277,6 +277,9 @@ enum mlx5_feature_name {\n /* NSH ITEM */\n #define MLX5_FLOW_ITEM_NSH (1ull << 53)\n \n+/* COMPARE ITEM */\n+#define MLX5_FLOW_ITEM_COMPARE (1ull << 54)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex c4a90a3690..82d7fa006f 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -426,6 +426,9 @@ flow_hw_matching_item_flags_get(const struct rte_flow_item items[])\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_COMPARE:\n+\t\t\tlast_item = MLX5_FLOW_ITEM_COMPARE;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\n@@ -4390,6 +4393,8 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t\t\trte_errno = EINVAL;\n \t\t\tgoto it_error;\n \t\t}\n+\t\tif (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)\n+\t\t\tmatcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;\n \t\tret = __atomic_fetch_add(&item_templates[i]->refcnt, 1,\n \t\t\t\t\t __ATOMIC_RELAXED) + 1;\n \t\tif (ret <= 1) {\n@@ -6670,6 +6675,66 @@ flow_hw_prepend_item(const struct rte_flow_item *items,\n \treturn copied_items;\n }\n \n+static inline bool\n+flow_hw_item_compare_field_supported(enum rte_flow_field_id field)\n+{\n+\tswitch (field) {\n+\tcase RTE_FLOW_FIELD_TAG:\n+\tcase RTE_FLOW_FIELD_META:\n+\tcase RTE_FLOW_FIELD_VALUE:\n+\t\treturn true;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn false;\n+}\n+\n+static int\n+flow_hw_validate_item_compare(const struct rte_flow_item *item,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_compare *comp_m = item->mask;\n+\tconst struct rte_flow_item_compare *comp_v = item->spec;\n+\n+\tif (unlikely(!comp_m))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL,\n+\t\t\t\t \"compare item mask is missing\");\n+\tif (comp_m->width != UINT32_MAX)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL,\n+\t\t\t\t \"compare item only support full mask\");\n+\tif (!flow_hw_item_compare_field_supported(comp_m->a.field) ||\n+\t !flow_hw_item_compare_field_supported(comp_m->b.field))\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL,\n+\t\t\t\t \"compare item field not support\");\n+\tif (comp_m->a.field == RTE_FLOW_FIELD_VALUE &&\n+\t comp_m->b.field == RTE_FLOW_FIELD_VALUE)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL,\n+\t\t\t\t \"compare between value is not valid\");\n+\tif (comp_v) {\n+\t\tif (comp_v->operation != comp_m->operation ||\n+\t\t comp_v->a.field != comp_m->a.field ||\n+\t\t comp_v->b.field != comp_m->b.field)\n+\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL,\n+\t\t\t\t\t \"compare item spec/mask not matching\");\n+\t\tif ((comp_v->width & comp_m->width) != 32)\n+\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL,\n+\t\t\t\t\t \"compare item only support full mask\");\n+\t}\n+\treturn 0;\n+}\n+\n static int\n flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_pattern_template_attr *attr,\n@@ -6680,6 +6745,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \tint i, tag_idx;\n \tbool items_end = false;\n \tuint32_t tag_bitmap = 0;\n+\tint ret;\n \n \tif (!attr->ingress && !attr->egress && !attr->transfer)\n \t\treturn rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n@@ -6817,6 +6883,13 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t\t \" attribute\");\n \t\t\tbreak;\n \t\t}\n+\t\tcase RTE_FLOW_ITEM_TYPE_COMPARE:\n+\t\t{\n+\t\t\tret = flow_hw_validate_item_compare(&items[i], error);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t\tbreak;\n+\t\t}\n \t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n \t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n \t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n", "prefixes": [ "v3", "3/3" ] }