Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/135842/?format=api
{ "id": 135842, "url": "http://patches.dpdk.org/api/patches/135842/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240111070043.1276161-6-gavinl@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240111070043.1276161-6-gavinl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240111070043.1276161-6-gavinl@nvidia.com", "date": "2024-01-11T07:00:43", "name": "[RFC,5/5] net/mlx5/hws: support VXLAN-GPE matching", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "649529190c37dab75947f9e9f067e8f7eb22059c", "submitter": { "id": 3217, "url": "http://patches.dpdk.org/api/people/3217/?format=api", "name": "Gavin Li", "email": "gavinl@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240111070043.1276161-6-gavinl@nvidia.com/mbox/", "series": [ { "id": 30782, "url": "http://patches.dpdk.org/api/series/30782/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30782", "date": "2024-01-11T07:00:39", "name": "support VXLAN-GPE header fields(flags, rsvd0 and rsvd1) matching", "version": 1, "mbox": "http://patches.dpdk.org/series/30782/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135842/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/135842/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 63C4D4388E;\n\tThu, 11 Jan 2024 08:01:59 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1769740A6D;\n\tThu, 11 Jan 2024 08:01:44 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69])\n by mails.dpdk.org (Postfix) with ESMTP id E34F3406BA\n for <dev@dpdk.org>; Thu, 11 Jan 2024 08:01:42 +0100 (CET)", "from MW3PR05CA0010.namprd05.prod.outlook.com (2603:10b6:303:2b::15)\n by CH0PR12MB5387.namprd12.prod.outlook.com (2603:10b6:610:d6::17)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.18; Thu, 11 Jan\n 2024 07:01:40 +0000", "from MWH0EPF000989EC.namprd02.prod.outlook.com\n (2603:10b6:303:2b:cafe::b6) by MW3PR05CA0010.outlook.office365.com\n (2603:10b6:303:2b::15) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.12 via Frontend\n Transport; Thu, 11 Jan 2024 07:01:40 +0000", "from mail.nvidia.com (216.228.117.161) by\n MWH0EPF000989EC.mail.protection.outlook.com (10.167.241.139) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7181.14 via Frontend Transport; Thu, 11 Jan 2024 07:01:39 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 10 Jan\n 2024 23:01:21 -0800", "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 10 Jan\n 2024 23:01:17 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=ZmZywgPYoswUQ9Z+GHYtWEn52n3+Tg3hXBtEVJwc6JzGzCnEAkIccxgELnC2Ghcsb1hB9qTPBCBFYnvEhlQHuLJBPcmRAJ3uyqS21Da/kpMMmFhiGFxvdjeaVe0LMP8SbZwCAFfDdI7nuHWmq4wDgLajvAdjEHPb+bpe9vAUZTGRE/awxR1WsxjFPBVEJDwaXlvkjG4VYCSePrx9y1kHXwqzx2igK/G+mzDRe4PD4hnSs9tyTp9xY/xLYUNANTp8Jbp53AF61wJaYthkIXXB5HEYdQjwvmH6wk3XbTna7VmJ3N4lz87RqMHnkfs+DiOgKERghuSdbxtW4HIwICa5Cg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=dzoQXYF+YSsnR7uwtZrr3CJrsWfP2K68Zw+835E3qLE=;\n b=LHNISLQe9o78QYZ6WdTfLHjtXuQF8t008+p49z2qisxeSS4l280Vmm2eUFAieF+e7JnHe38pOgHow/wzAcTuR+Wpsmu0goIs2GTP87pDK8JswRrjWxkMNwOCk6QOxNzsB/M68ONiUN/7mw4Jxa5HJANRex+1L3omTYyoij+7oZK95RKFxUztWMJ7cS0kaDIPmEZTXGaGaM2KEzt1TNdAW2qDTRNzFfthssvD8rwaZMGmhHiKFLK14lJwJDYZRVQbWs2nmxP5E1bdNFk7VyUns+Em675LzocG6XLINoGhgT+W/w4t80JfNvJlXXEznxFYaLGLi2yJmPKRsr4AIJKwiA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=dzoQXYF+YSsnR7uwtZrr3CJrsWfP2K68Zw+835E3qLE=;\n b=Aq1CtxGhMmlBeivl5V5p5TnqRq8aW/pnWbXgYY88Egpw9/zZ4pWrUj4Sfg+53shI1ruwdQXlZi10JueKfgYe5VK3dbAFxVL5DOkVTMl0svC91iY1Jwka2OwzJExvDbb/qFozM9s2c20Hbe7HOoIwrSEqgTWl3PsrozMKu7+aweRLTQYyYqBmpMhq2iWOxayVBcOamGI2/vrkYLCVjuI1VHhGMAC7ME7hUVBZgel6nHZi7ndFsxxUoYWwbKbFOjsQO7DRHc0rKtk2AYWdCE7rUJ2F7Tm4LRLH1XGbcUbExACXtpkF4tfboOODyCQ5CaKn+f/NaRJBhqU2U75uQDd3ag==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Gavin Li <gavinl@nvidia.com>", "To": "<dev@dpdk.org>, <thomas@monjalon.net>, <orika@nvidia.com>,\n <aman.deep.singh@intel.com>, <yuying.zhang@intel.com>,\n <dsosnowski@nvidia.com>, <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>,\n <matan@nvidia.com>", "CC": "<jiaweiw@nvidia.com>, <rasland@nvidia.com>, Itamar Gozlan\n <igozlan@nvidia.com>", "Subject": "[RFC 5/5] net/mlx5/hws: support VXLAN-GPE matching", "Date": "Thu, 11 Jan 2024 09:00:43 +0200", "Message-ID": "<20240111070043.1276161-6-gavinl@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240111070043.1276161-1-gavinl@nvidia.com>", "References": "<20240111070043.1276161-1-gavinl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000989EC:EE_|CH0PR12MB5387:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2ef23e59-dd94-46f4-3663-08dc127328fb", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n rdwB4Bnl6z5Y32r7AvcbjK9uO1Y+HV+tR3Dag78pvunh8lCJzoQfVjmrScCBtQ3mYoaacXGEAPVl8MorbozJBMaR8WO+vsq4K2/VUU9igrTOWEg0PBJiQXNQoepCRnW22Ov4VzZZV+Qm3epP3AvBcmo2GICaocQE9ic09IyPeK967Fw6irwl+Rfj4K/yxMnzmv0rfLhB6V8hJaqTZ+wRK9RESArkyfvxHox9AOuMJfTC2lQHUxNJVt5Jk3Q2FHUkyZGbHyA3MOOcrxZNhWOPZVlK/p00HARnPNhphQnPE8nOp4bkUVWBeh0TvsP28VhBfybLz36ga+A/SY3unxnX2sFUu5nc79mRrW0k88DehovDhfOh8pdp+erk947P5GQzsfVN7MgC4IungP0x8O1GyGQrOjmHQawdlJ2RZM/21KMlUrF9qYU6kgfcieAGYmDeEtCpJ22f3o0TP0Q97ep06qrpBSuHWYKRiT/TwSx3GdEj5PX3lgYz70pV+UzjnehwWEJAzTJ1XJptCLtNWwfhgaqxMCgNNf/DTNiT9uW3oE6KR5lI7nwlbMTWR1malO/meRsskUYNvto+iNvWz2dAmd60wqFLpHnuwZM+C9PlOM1nZ6yArTtFWZ2zcVC3BSD6oh0fWvIDGShSsppu0JBh/LtaYQ+2kmhZUnGLAtIdd1tU2+4VCUA5IA5cREDl7YOtVY0srTx1TRkM7kpHekApIl1bgdLKXfAE7zkPbCHutYA1LSrtPb5axwoUcXFeNGoY", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(346002)(136003)(376002)(396003)(230922051799003)(1800799012)(451199024)(82310400011)(64100799003)(186009)(46966006)(40470700004)(36840700001)(40460700003)(40480700001)(55016003)(47076005)(110136005)(86362001)(36756003)(7636003)(356005)(36860700001)(82740400003)(8676002)(4326008)(83380400001)(2616005)(26005)(1076003)(107886003)(426003)(16526019)(336012)(6286002)(6666004)(7696005)(70206006)(54906003)(316002)(70586007)(6636002)(478600001)(5660300002)(41300700001)(2906002)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "11 Jan 2024 07:01:39.6452 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2ef23e59-dd94-46f4-3663-08dc127328fb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989EC.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH0PR12MB5387", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for matching VXLAN-GPE tunnel header.\n\nSigned-off-by: Gavin Li <gavinl@nvidia.com>\nReviewed-by: Itamar Gozlan <igozlan@nvidia.com>\nReviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n doc/guides/rel_notes/release_24_03.rst | 6 ++\n drivers/net/mlx5/hws/mlx5dr_definer.c | 117 +++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 13 +++\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 4 files changed, 137 insertions(+)", "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 2c0e2930cc..d5e1b1ad37 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -59,6 +59,12 @@ New Features\n \n * Added support for accumulating from src field to dst field.\n \n+ * Added support for VXLAN-GPE flags/rsvd0/rsvd fields matching in DV flow\n+ engine (``dv_flow_en`` = 1).\n+\n+ * Added support for VXLAN-GPE matching in HW Steering flow engine\n+ (``dv_flow_en`` = 2).\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 0b60479406..8958049c8f 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -9,6 +9,7 @@\n #define ETH_TYPE_IPV4_VXLAN\t0x0800\n #define ETH_TYPE_IPV6_VXLAN\t0x86DD\n #define ETH_VXLAN_DEFAULT_PORT\t4789\n+#define ETH_VXLAN_GPE_DEFAULT_PORT\t4790\n #define IP_UDP_PORT_MPLS\t6635\n #define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n@@ -167,6 +168,10 @@ struct mlx5dr_definer_conv_data {\n \tX(SET,\t\tgtp_ext_hdr_qfi,\tv->hdr.qfi,\t\trte_flow_item_gtp_psc) \\\n \tX(SET,\t\tvxlan_flags,\t\tv->flags,\t\trte_flow_item_vxlan) \\\n \tX(SET,\t\tvxlan_udp_port,\t\tETH_VXLAN_DEFAULT_PORT,\trte_flow_item_vxlan) \\\n+\tX(SET,\t\tvxlan_gpe_udp_port,\tETH_VXLAN_GPE_DEFAULT_PORT,\trte_flow_item_vxlan_gpe) \\\n+\tX(SET,\t\tvxlan_gpe_flags,\tv->flags,\t\trte_flow_item_vxlan_gpe) \\\n+\tX(SET,\t\tvxlan_gpe_protocol,\tv->protocol,\t\trte_flow_item_vxlan_gpe) \\\n+\tX(SET,\t\tvxlan_gpe_rsvd1,\tv->rsvd1,\t\trte_flow_item_vxlan_gpe) \\\n \tX(SET,\t\tmpls_udp_port,\t\tIP_UDP_PORT_MPLS,\trte_flow_item_mpls) \\\n \tX(SET,\t\tsource_qp,\t\tv->queue,\t\tmlx5_rte_flow_item_sq) \\\n \tX(SET,\t\ttag,\t\t\tv->data,\t\trte_flow_item_tag) \\\n@@ -691,6 +696,28 @@ mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp));\n }\n \n+static void\n+mlx5dr_definer_vxlan_gpe_vni_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_vxlan_gpe *v = item_spec;\n+\n+\tmemcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));\n+}\n+\n+static void\n+mlx5dr_definer_vxlan_gpe_rsvd0_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_vxlan_gpe *v = item_spec;\n+\tuint16_t rsvd0;\n+\n+\trsvd0 = (v->rsvd0[0] << 8 | v->rsvd0[1]);\n+\tDR_SET(tag, rsvd0, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n static int\n mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -2385,6 +2412,92 @@ mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_vxlan_gpe(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\t struct rte_flow_item *item,\n+\t\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_vxlan_gpe *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\tif (inner) {\n+\t\tDR_LOG(ERR, \"Inner VXLAN GPE item not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\t/* In order to match on VXLAN GPE we must match on ip_protocol and l4_dport */\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_udp_protocol_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_udp_port_set;\n+\t\t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n+\t\t}\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->flags) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_flags_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, flags);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, flags);\n+\t}\n+\n+\tif (!is_mem_zero(m->rsvd0, 2)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd0_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd0);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd0);\n+\t}\n+\n+\tif (m->protocol) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_protocol_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->byte_off += MLX5_BYTE_OFF(header_vxlan_gpe, protocol);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, protocol);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, protocol);\n+\t}\n+\n+\tif (!is_mem_zero(m->vni, 3)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_vni_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, vni);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, vni);\n+\t}\n+\n+\tif (m->rsvd1) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd1_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd1);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_match_template *mt,\n@@ -2537,6 +2650,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_ptype(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_PTYPE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n+\t\t\tret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex 6f1c99e37a..3dc5f4438d 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -91,6 +91,11 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_VPORT_REG_C_0,\n \tMLX5DR_DEFINER_FNAME_VXLAN_FLAGS,\n \tMLX5DR_DEFINER_FNAME_VXLAN_VNI,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1,\n \tMLX5DR_DEFINER_FNAME_SOURCE_QP,\n \tMLX5DR_DEFINER_FNAME_REG_0,\n \tMLX5DR_DEFINER_FNAME_REG_1,\n@@ -593,6 +598,14 @@ struct mlx5_ifc_header_vxlan_bits {\n \tu8 reserved2[0x8];\n };\n \n+struct mlx5_ifc_header_vxlan_gpe_bits {\n+\tu8 flags[0x8];\n+\tu8 rsvd0[0x10];\n+\tu8 protocol[0x8];\n+\tu8 vni[0x18];\n+\tu8 rsvd1[0x8];\n+};\n+\n struct mlx5_ifc_header_gre_bits {\n \tunion {\n \t\tu8 c_rsvd0_ver[0x10];\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex c4a90a3690..6d8f4f8f8b 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -6827,6 +6827,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n+\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n \t\tcase RTE_FLOW_ITEM_TYPE_MPLS:\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE:\n", "prefixes": [ "RFC", "5/5" ] }