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GET /api/patches/135839/?format=api
{ "id": 135839, "url": "http://patches.dpdk.org/api/patches/135839/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240111070043.1276161-4-gavinl@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240111070043.1276161-4-gavinl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240111070043.1276161-4-gavinl@nvidia.com", "date": "2024-01-11T07:00:41", "name": "[RFC,3/5] net/mlx5: support VXLAN-GPE reserved fields matching", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d9d3c95a7633d538d0d4f61eb32946879dd2df98", "submitter": { "id": 3217, "url": "http://patches.dpdk.org/api/people/3217/?format=api", "name": "Gavin Li", "email": "gavinl@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240111070043.1276161-4-gavinl@nvidia.com/mbox/", "series": [ { "id": 30782, "url": "http://patches.dpdk.org/api/series/30782/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30782", "date": "2024-01-11T07:00:39", "name": "support VXLAN-GPE header fields(flags, rsvd0 and rsvd1) matching", "version": 1, "mbox": "http://patches.dpdk.org/series/30782/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135839/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135839/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7AF624388E;\n\tThu, 11 Jan 2024 08:01:33 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 331D94067A;\n\tThu, 11 Jan 2024 08:01:28 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id C3227402F1\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gavin Li <gavinl@nvidia.com>", "To": "<dev@dpdk.org>, <thomas@monjalon.net>, <orika@nvidia.com>,\n <aman.deep.singh@intel.com>, <yuying.zhang@intel.com>,\n <dsosnowski@nvidia.com>, <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>,\n <matan@nvidia.com>", "CC": "<jiaweiw@nvidia.com>, <rasland@nvidia.com>", "Subject": "[RFC 3/5] net/mlx5: support VXLAN-GPE reserved fields matching", "Date": "Thu, 11 Jan 2024 09:00:41 +0200", "Message-ID": "<20240111070043.1276161-4-gavinl@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240111070043.1276161-1-gavinl@nvidia.com>", "References": "<20240111070043.1276161-1-gavinl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF000001CA:EE_|BY5PR12MB4869:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3f53bcea-2606-47a9-cc31-08dc12731f9d", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n VKR0N6pkTLoVLMQfGeclZLmsjgHaSBbvafBfQYMztmMCn4h+780JetN86uKULfGXdf+PsMJCq5CYdh/uCPggg0HpH5pEngLl0yDzkSHyfCohWapEYoKLM/e+XpjsjKZ/kJidRKCSK82cnYJu0Rrj5DzrjNhQFUYiUuAv8HGxjldn5q7N9nowBey6xh7GBWHOFLMYRMgqA9t6CcqVvxxuu/aunSWC/gJP337ffjyU91Cq3r26PtG5W0CgXQlSZDVGual0bDZmXcwizLgezzGzJxgOSqmRUM0LwcdoPnVATdKozst4vP7OYzs0Y8hl7yiV8yvh0CPKeTCdu6e4lmt5Ra/1VF+MbI5VlBr7Qz0aMpETOI8X0rOpmJEkZNKm6TCaXHxbetEmT9MuF0HzZQUBk6DTA80dwsX3gdYM5BpN9ErLmzD8ZCtC5d57G0aZC1u9A25jLbleetotu3JKnLit5m/uXZw1jm6cuNBopdcVoH2OmprFamwm3wzXSTVJn+l/PjV641PPlr62rzt3x6oy/LaBMfGeDqwS6+x5vs1a2PVBsBdBfmWrKVRK3HzWK9oBS14zJqnn0e51lUwkV0DOw9G/8wP/VbaOEwL0ObdUUGepuAvQl74UXMeQ/lmrzvohtmuyRGP6ECsCtWFXAUDlh73d1lhrFnmZplZdlxz+fyb3lKdmIMnoAGUr3Zpl4BzX3lCO4CHyr/99Qbm89wiiBw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(451199024)(64100799003)(1800799012)(186009)(82310400011)(46966006)(36840700001)(83380400001)(40480700001)(55016003)(47076005)(82740400003)(110136005)(316002)(478600001)(54906003)(7636003)(6636002)(70586007)(356005)(4326008)(5660300002)(8936002)(6666004)(7696005)(8676002)(36860700001)(107886003)(70206006)(26005)(2906002)(336012)(6286002)(41300700001)(16526019)(1076003)(2616005)(36756003)(86362001)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "11 Jan 2024 07:01:24.0429 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3f53bcea-2606-47a9-cc31-08dc12731f9d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SJ5PEPF000001CA.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4869", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This adds matching on the reserved fields of VXLAN-GPE header (the 16-bits\nbefore Next Protocol and the last 8-bits).\n\nTo support all the header fields, tunnel_header_0_1 should be supported by\nFW and misc5_cap is set.\n\nIf one of the reserved fields is matched on, misc5 is used for matching.\nOtherwise, keep using misc3\n\nSigned-off-by: Gavin Li <gavinl@nvidia.com>\nReviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 5 +++++\n drivers/net/mlx5/mlx5_flow.c | 5 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 32 ++++++++++++++++++++++++++------\n 3 files changed, 36 insertions(+), 6 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 7bfd6c6aeb..27384d5a86 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -311,6 +311,11 @@ Limitations\n Group zero's behavior may differ which depends on FW.\n Matching value equals 0 (value & mask) is not supported.\n \n+- Matching on VXLAN-GPE header fields:\n+\n+ - ``rsvd0``/``rsvd1`` matching support depends on FW version when using DV flow\n+ engine (``dv_flow_en`` = 1).\n+\n - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.\n \n - MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2).\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex ffa183dc1b..9b6f483d3f 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -3316,6 +3316,11 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,\n \t\t\t\t\t \"no outer UDP layer found\");\n \tif (!mask)\n \t\tmask = &rte_flow_item_vxlan_gpe_mask;\n+\tif (priv->sh->misc5_cap && priv->sh->tunnel_header_0_1) {\n+\t\tnic_mask.rsvd0[0] = 0xff;\n+\t\tnic_mask.rsvd0[1] = 0xff;\n+\t\tnic_mask.rsvd1 = 0xff;\n+\t}\n \tret = mlx5_flow_item_acceptable\n \t\t(item, (const uint8_t *)mask,\n \t\t (const uint8_t *)&nic_mask,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 97f55003c3..f3589da654 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9813,14 +9813,10 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,\n \t\tvxlan_v = vxlan_m;\n \telse if (key_type == MLX5_SET_MATCHER_HS_V)\n \t\tvxlan_m = vxlan_v;\n-\tfor (i = 0; i < size; ++i)\n-\t\tvni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];\n \tif (vxlan_m->hdr.flags) {\n \t\tflags_m = vxlan_m->hdr.flags;\n \t\tflags_v = vxlan_v->hdr.flags;\n \t}\n-\tMLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags,\n-\t\t flags_m & flags_v);\n \tm_protocol = vxlan_m->hdr.protocol;\n \tv_protocol = vxlan_v->hdr.protocol;\n \tif (!m_protocol) {\n@@ -9839,8 +9835,32 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,\n \t\tif (key_type & MLX5_SET_MATCHER_M)\n \t\t\tv_protocol = m_protocol;\n \t}\n-\tMLX5_SET(fte_match_set_misc3, misc_v,\n-\t\t outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);\n+\t/*\n+\t * If only match flags/protocol/vni field, keep using misc3 for matching.\n+\t * If need to match rsvd0 or rsvd1, using misc5 and do not need using misc3.\n+\t */\n+\tif (!(vxlan_m->hdr.rsvd0[0] || vxlan_m->hdr.rsvd0[1] || vxlan_m->hdr.rsvd1)) {\n+\t\tfor (i = 0; i < size; ++i)\n+\t\t\tvni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];\n+\t\tMLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags,\n+\t\t\t flags_m & flags_v);\n+\t\tMLX5_SET(fte_match_set_misc3, misc_v,\n+\t\t\t outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);\n+\t} else {\n+\t\tuint32_t tunnel_v;\n+\t\tvoid *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);\n+\n+\t\ttunnel_v = (flags_m & flags_v) << 24 |\n+\t\t\t (vxlan_v->hdr.rsvd0[0] & vxlan_m->hdr.rsvd0[0]) << 16 |\n+\t\t\t (vxlan_v->hdr.rsvd0[1] & vxlan_m->hdr.rsvd0[1]) << 8 |\n+\t\t\t (m_protocol & v_protocol);\n+\t\tMLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0, tunnel_v);\n+\t\ttunnel_v = (vxlan_v->hdr.vni[0] & vxlan_m->hdr.vni[0]) << 24 |\n+\t\t\t (vxlan_v->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 16 |\n+\t\t\t (vxlan_v->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 8 |\n+\t\t\t (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1);\n+\t\tMLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, tunnel_v);\n+\t}\n }\n \n /**\n", "prefixes": [ "RFC", "3/5" ] }