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GET /api/patches/135454/?format=api
{ "id": 135454, "url": "http://patches.dpdk.org/api/patches/135454/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231221123545.510-25-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231221123545.510-25-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231221123545.510-25-anoobj@marvell.com", "date": "2023-12-21T12:35:45", "name": "[24/24] crypto/cnxk: add CPT SG mode debug", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "defcccd0fcd168964ed9325506817503aabadc40", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231221123545.510-25-anoobj@marvell.com/mbox/", "series": [ { "id": 30646, "url": "http://patches.dpdk.org/api/series/30646/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30646", "date": "2023-12-21T12:35:21", "name": "Fixes and improvements in crypto cnxk", "version": 1, "mbox": "http://patches.dpdk.org/series/30646/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135454/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/135454/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 09D3343750;\n\tThu, 21 Dec 2023 13:38:47 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 87B3542EE4;\n\tThu, 21 Dec 2023 13:37:03 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 001E942EC0\n for <dev@dpdk.org>; Thu, 21 Dec 2023 13:36:55 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 3BLCVS3A019305 for <dev@dpdk.org>; Thu, 21 Dec 2023 04:36:55 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v4nekg0k0-5\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 21 Dec 2023 04:36:55 -0800 (PST)", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 21 Dec 2023 04:36:53 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 21 Dec 2023 04:36:53 -0800", "from BG-LT92004.corp.innovium.com (unknown [10.193.71.152])\n by maili.marvell.com (Postfix) with ESMTP id 08C993F7079;\n Thu, 21 Dec 2023 04:36:50 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=xSH6zysELKxU8qenaBD+enUz6xsWOZ2Km2Fe7L9VYMw=; b=hpc\n l2FcEgUUuMPfHTSRoZ5FR25+m0B1M+70xSD3mNzPvYZgIeO4TnaGimfdDbYXhr9I\n HR7mNorLaYaDbKCsceUjG8F/lCKzBNmM594EPZr5N02I+CBaa4KCdcPA0V4x0sos\n NILKVldGkx/CrAyvLoA6GXSowcMGvPm0F5o1Hq5uHh6SCCySdhB55SUPU0rxeZjN\n ZcO+oarHaFqx5F4s3RpywsYpIXqJgdAMpyY3W+iuuWxruOECzl/E45UdMTcf6gza\n Zlcxh4M2nfNTuRPZ559SZQtUp2as725QIoPPyGgIQrJuJgN31KW9kKhJ+skSFDOQ\n I0TEpvaZzN0RrbCVPpg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Vidya Sagar Velumuri <vvelumuri@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 24/24] crypto/cnxk: add CPT SG mode debug", "Date": "Thu, 21 Dec 2023 18:05:45 +0530", "Message-ID": "<20231221123545.510-25-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231221123545.510-1-anoobj@marvell.com>", "References": "<20231221123545.510-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "c239U0MNB_YgsRS6XT-1gLqAuvlyqbyi", "X-Proofpoint-ORIG-GUID": "c239U0MNB_YgsRS6XT-1gLqAuvlyqbyi", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Tejasree Kondoj <ktejasree@marvell.com>\n\nAdding CPT SG mode debug dump.\n\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 135 +++++++++++++++++++++-\n drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 7 ++\n 2 files changed, 141 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex c350371505..6cfcbafdcc 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -2,9 +2,10 @@\n * Copyright(C) 2021 Marvell.\n */\n \n-#include <rte_cryptodev.h>\n #include <cryptodev_pmd.h>\n+#include <rte_cryptodev.h>\n #include <rte_event_crypto_adapter.h>\n+#include <rte_hexdump.h>\n #include <rte_ip.h>\n \n #include <ethdev_driver.h>\n@@ -103,6 +104,104 @@ cpt_sec_ipsec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \treturn ret;\n }\n \n+#ifdef CPT_INST_DEBUG_ENABLE\n+static inline void\n+cpt_request_data_sgv2_mode_dump(uint8_t *in_buffer, bool glist, uint16_t components)\n+{\n+\tstruct roc_se_buf_ptr list_ptr[ROC_MAX_SG_CNT];\n+\tconst char *list = glist ? \"glist\" : \"slist\";\n+\tstruct roc_sg2list_comp *sg_ptr = NULL;\n+\tuint16_t list_cnt = 0;\n+\tchar suffix[64];\n+\tint i, j;\n+\n+\tsg_ptr = (void *)in_buffer;\n+\tfor (i = 0; i < components; i++) {\n+\t\tfor (j = 0; j < sg_ptr->u.s.valid_segs; j++) {\n+\t\t\tlist_ptr[i * 3 + j].size = sg_ptr->u.s.len[j];\n+\t\t\tlist_ptr[i * 3 + j].vaddr = (void *)sg_ptr->ptr[j];\n+\t\t\tlist_ptr[i * 3 + j].vaddr = list_ptr[i * 3 + j].vaddr;\n+\t\t\tlist_cnt++;\n+\t\t}\n+\t\tsg_ptr++;\n+\t}\n+\n+\tprintf(\"Current %s: %u\\n\", list, list_cnt);\n+\n+\tfor (i = 0; i < list_cnt; i++) {\n+\t\tsnprintf(suffix, sizeof(suffix), \"%s[%d]: vaddr 0x%\" PRIx64 \", vaddr %p len %u\",\n+\t\t\t list, i, (uint64_t)list_ptr[i].vaddr, list_ptr[i].vaddr, list_ptr[i].size);\n+\t\trte_hexdump(stdout, suffix, list_ptr[i].vaddr, list_ptr[i].size);\n+\t}\n+}\n+\n+static inline void\n+cpt_request_data_sg_mode_dump(uint8_t *in_buffer, bool glist)\n+{\n+\tstruct roc_se_buf_ptr list_ptr[ROC_MAX_SG_CNT];\n+\tconst char *list = glist ? \"glist\" : \"slist\";\n+\tstruct roc_sglist_comp *sg_ptr = NULL;\n+\tuint16_t list_cnt, components;\n+\tchar suffix[64];\n+\tint i;\n+\n+\tsg_ptr = (void *)(in_buffer + 8);\n+\tlist_cnt = rte_be_to_cpu_16((((uint16_t *)in_buffer)[2]));\n+\tif (!glist) {\n+\t\tcomponents = list_cnt / 4;\n+\t\tif (list_cnt % 4)\n+\t\t\tcomponents++;\n+\t\tsg_ptr += components;\n+\t\tlist_cnt = rte_be_to_cpu_16((((uint16_t *)in_buffer)[3]));\n+\t}\n+\n+\tprintf(\"Current %s: %u\\n\", list, list_cnt);\n+\tcomponents = list_cnt / 4;\n+\tfor (i = 0; i < components; i++) {\n+\t\tlist_ptr[i * 4 + 0].size = rte_be_to_cpu_16(sg_ptr->u.s.len[0]);\n+\t\tlist_ptr[i * 4 + 1].size = rte_be_to_cpu_16(sg_ptr->u.s.len[1]);\n+\t\tlist_ptr[i * 4 + 2].size = rte_be_to_cpu_16(sg_ptr->u.s.len[2]);\n+\t\tlist_ptr[i * 4 + 3].size = rte_be_to_cpu_16(sg_ptr->u.s.len[3]);\n+\t\tlist_ptr[i * 4 + 0].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[0]);\n+\t\tlist_ptr[i * 4 + 1].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[1]);\n+\t\tlist_ptr[i * 4 + 2].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[2]);\n+\t\tlist_ptr[i * 4 + 3].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[3]);\n+\t\tlist_ptr[i * 4 + 0].vaddr = list_ptr[i * 4 + 0].vaddr;\n+\t\tlist_ptr[i * 4 + 1].vaddr = list_ptr[i * 4 + 1].vaddr;\n+\t\tlist_ptr[i * 4 + 2].vaddr = list_ptr[i * 4 + 2].vaddr;\n+\t\tlist_ptr[i * 4 + 3].vaddr = list_ptr[i * 4 + 3].vaddr;\n+\t\tsg_ptr++;\n+\t}\n+\n+\tcomponents = list_cnt % 4;\n+\tswitch (components) {\n+\tcase 3:\n+\t\tlist_ptr[i * 4 + 2].size = rte_be_to_cpu_16(sg_ptr->u.s.len[2]);\n+\t\tlist_ptr[i * 4 + 2].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[2]);\n+\t\tlist_ptr[i * 4 + 2].vaddr = list_ptr[i * 4 + 2].vaddr;\n+\t\t/* FALLTHROUGH */\n+\tcase 2:\n+\t\tlist_ptr[i * 4 + 1].size = rte_be_to_cpu_16(sg_ptr->u.s.len[1]);\n+\t\tlist_ptr[i * 4 + 1].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[1]);\n+\t\tlist_ptr[i * 4 + 1].vaddr = list_ptr[i * 4 + 1].vaddr;\n+\t\t/* FALLTHROUGH */\n+\tcase 1:\n+\t\tlist_ptr[i * 4 + 0].size = rte_be_to_cpu_16(sg_ptr->u.s.len[0]);\n+\t\tlist_ptr[i * 4 + 0].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[0]);\n+\t\tlist_ptr[i * 4 + 0].vaddr = list_ptr[i * 4 + 0].vaddr;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i < list_cnt; i++) {\n+\t\tsnprintf(suffix, sizeof(suffix), \"%s[%d]: vaddr 0x%\" PRIx64 \", vaddr %p len %u\",\n+\t\t\t list, i, (uint64_t)list_ptr[i].vaddr, list_ptr[i].vaddr, list_ptr[i].size);\n+\t\trte_hexdump(stdout, suffix, list_ptr[i].vaddr, list_ptr[i].size);\n+\t}\n+}\n+#endif\n+\n static __rte_always_inline int __rte_hot\n cpt_sec_tls_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \t\t struct cn10k_sec_session *sess, struct cpt_inst_s *inst,\n@@ -205,6 +304,31 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct\n \n \tinst[0].w7.u64 = w7;\n \n+#ifdef CPT_INST_DEBUG_ENABLE\n+\tinfl_req->dptr = (uint8_t *)inst[0].dptr;\n+\tinfl_req->rptr = (uint8_t *)inst[0].rptr;\n+\tinfl_req->is_sg_ver2 = is_sg_ver2;\n+\tinfl_req->scatter_sz = inst[0].w6.s.scatter_sz;\n+\tinfl_req->opcode_major = inst[0].w4.s.opcode_major;\n+\n+\trte_hexdump(stdout, \"cptr\", (void *)(uint64_t)inst[0].w7.s.cptr, 128);\n+\tprintf(\"major opcode:%d\\n\", inst[0].w4.s.opcode_major);\n+\tprintf(\"minor opcode:%d\\n\", inst[0].w4.s.opcode_minor);\n+\tprintf(\"param1:%d\\n\", inst[0].w4.s.param1);\n+\tprintf(\"param2:%d\\n\", inst[0].w4.s.param2);\n+\tprintf(\"dlen:%d\\n\", inst[0].w4.s.dlen);\n+\n+\tif (is_sg_ver2) {\n+\t\tcpt_request_data_sgv2_mode_dump((void *)inst[0].dptr, 1, inst[0].w5.s.gather_sz);\n+\t\tcpt_request_data_sgv2_mode_dump((void *)inst[0].rptr, 0, inst[0].w6.s.scatter_sz);\n+\t} else {\n+\t\tif (infl_req->opcode_major >> 7) {\n+\t\t\tcpt_request_data_sg_mode_dump((void *)inst[0].dptr, 1);\n+\t\t\tcpt_request_data_sg_mode_dump((void *)inst[0].dptr, 0);\n+\t\t}\n+\t}\n+#endif\n+\n \treturn 1;\n }\n \n@@ -935,6 +1059,15 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop\n \t}\n \n \tif (likely(compcode == CPT_COMP_GOOD)) {\n+#ifdef CPT_INST_DEBUG_ENABLE\n+\t\tif (infl_req->is_sg_ver2)\n+\t\t\tcpt_request_data_sgv2_mode_dump(infl_req->rptr, 0, infl_req->scatter_sz);\n+\t\telse {\n+\t\t\tif (infl_req->opcode_major >> 7)\n+\t\t\t\tcpt_request_data_sg_mode_dump(infl_req->dptr, 0);\n+\t\t}\n+#endif\n+\n \t\tif (unlikely(uc_compcode)) {\n \t\t\tif (uc_compcode == ROC_SE_ERR_GC_ICV_MISCOMPARE)\n \t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\nindex c6bb8023ea..e7bba25cb8 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n@@ -51,6 +51,13 @@ struct cpt_inflight_req {\n \t};\n \tvoid *mdata;\n \tuint8_t op_flags;\n+#ifdef CPT_INST_DEBUG_ENABLE\n+\tuint8_t scatter_sz;\n+\tuint8_t opcode_major;\n+\tuint8_t is_sg_ver2;\n+\tuint8_t *dptr;\n+\tuint8_t *rptr;\n+#endif\n \tvoid *qp;\n } __rte_aligned(ROC_ALIGN);\n \n", "prefixes": [ "24/24" ] }