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GET /api/patches/135339/?format=api
{ "id": 135339, "url": "http://patches.dpdk.org/api/patches/135339/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231219155124.4133385-4-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231219155124.4133385-4-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231219155124.4133385-4-ciara.power@intel.com", "date": "2023-12-19T15:51:22", "name": "[3/4] crypto/qat: add new gen3 CMAC macros", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "16a75575685182715f5d12b3fd16b1e4bd93c442", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231219155124.4133385-4-ciara.power@intel.com/mbox/", "series": [ { "id": 30615, "url": "http://patches.dpdk.org/api/series/30615/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30615", "date": "2023-12-19T15:51:19", "name": "add new QAT gen3 device", "version": 1, "mbox": "http://patches.dpdk.org/series/30615/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135339/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135339/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C0EF843746;\n\tTue, 19 Dec 2023 16:51:57 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E3B5442E2E;\n\tTue, 19 Dec 2023 16:51:40 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id E7E8A42E1C\n for <dev@dpdk.org>; Tue, 19 Dec 2023 16:51:37 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Dec 2023 07:51:37 -0800", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.80])\n by orsmga002.jf.intel.com with ESMTP; 19 Dec 2023 07:51:36 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1703001098; x=1734537098;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=+5mHi7X1wkNZGbjGhYOf2tJjZHSnTHlc9JwBdPIjIAw=;\n b=commZ7ioYUbfwy0Fut1hthFWFpqHppqKGTozDkNxyFD51R4AdIzFh7RI\n NmuGSVRKdpKLE107PB3jymdY+av0vzT/yY1bAsLrG5ABgBxrhycYkG6pT\n pk259RZR2XDRrkrIBbu4MaIdbuQWauDq8sgpKJUbQNU3/C4/3CweRVOdS\n IzVMC2eepMmst0eA5Z6dErRzbcheM/sEcnFYcibiW+VSfgGUsFnNxLqUB\n Qduj8GyW2iQRomPnL3gYScj4oZroxPo5zCcLc3eQGcHMWfWe4CI2zdOX9\n 34SnLrqow1li2AnoFk2PQzFaQ4RqinleGOHGFmxznXdt1HR+phJflNnoX w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10929\"; a=\"399510255\"", "E=Sophos;i=\"6.04,288,1695711600\"; d=\"scan'208\";a=\"399510255\"", "E=McAfee;i=\"6600,9927,10929\"; a=\"776021693\"", "E=Sophos;i=\"6.04,288,1695711600\"; d=\"scan'208\";a=\"776021693\"" ], "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "Ciara Power <ciara.power@intel.com>,\n\tKai Ji <kai.ji@intel.com>", "Subject": "[PATCH 3/4] crypto/qat: add new gen3 CMAC macros", "Date": "Tue, 19 Dec 2023 15:51:22 +0000", "Message-Id": "<20231219155124.4133385-4-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231219155124.4133385-1-ciara.power@intel.com>", "References": "<20231219155124.4133385-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The new QAT GEN3 device uses new macros for CMAC values, rather than\nusing XCBC_MAC ones.\n\nThe wireless slice handles CMAC in the new gen3 device, and no key\nprecomputes are required by SW.\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/common/qat/qat_adf/icp_qat_hw.h | 4 +++-\n drivers/crypto/qat/qat_sym_session.c | 28 +++++++++++++++++++++----\n 2 files changed, 27 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h\nindex dfd0ea133c..b0a6126271 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_hw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h\n@@ -74,7 +74,7 @@ enum icp_qat_hw_auth_algo {\n \tICP_QAT_HW_AUTH_ALGO_RESERVED = 20,\n \tICP_QAT_HW_AUTH_ALGO_RESERVED1 = 21,\n \tICP_QAT_HW_AUTH_ALGO_RESERVED2 = 22,\n-\tICP_QAT_HW_AUTH_ALGO_RESERVED3 = 22,\n+\tICP_QAT_HW_AUTH_ALGO_AES_128_CMAC = 22,\n \tICP_QAT_HW_AUTH_ALGO_RESERVED4 = 23,\n \tICP_QAT_HW_AUTH_ALGO_RESERVED5 = 24,\n \tICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 = 25,\n@@ -179,6 +179,7 @@ struct icp_qat_hw_auth_setup {\n #define ICP_QAT_HW_ZUC_256_MAC_32_STATE1_SZ 8\n #define ICP_QAT_HW_ZUC_256_MAC_64_STATE1_SZ 8\n #define ICP_QAT_HW_ZUC_256_MAC_128_STATE1_SZ 16\n+#define ICP_QAT_HW_AES_CMAC_STATE1_SZ 16\n \n #define ICP_QAT_HW_NULL_STATE2_SZ 32\n #define ICP_QAT_HW_MD5_STATE2_SZ 16\n@@ -207,6 +208,7 @@ struct icp_qat_hw_auth_setup {\n #define ICP_QAT_HW_GALOIS_H_SZ 16\n #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8\n #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16\n+#define ICP_QAT_HW_AES_128_CMAC_STATE2_SZ 16\n \n struct icp_qat_hw_auth_sha512 {\n \tstruct icp_qat_hw_auth_setup inner_setup;\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex ebdad0bd67..b1649b8d18 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -922,11 +922,20 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_AES_CMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n \t\tsession->aes_cmac = 1;\n-\t\tif (internals->qat_dev->has_wireless_slice) {\n-\t\t\tis_wireless = 1;\n-\t\t\tsession->is_wireless = 1;\n+\t\tif (!internals->qat_dev->has_wireless_slice) {\n+\t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n+\t\t\tbreak;\n+\t\t}\n+\t\tis_wireless = 1;\n+\t\tsession->is_wireless = 1;\n+\t\tswitch (key_length) {\n+\t\tcase ICP_QAT_HW_AES_128_KEY_SZ:\n+\t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tQAT_LOG(ERR, \"Invalid key length: %d\", key_length);\n+\t\t\treturn -ENOTSUP;\n \t\t}\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_AES_GMAC:\n@@ -1309,6 +1318,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n \tcase ICP_QAT_HW_AUTH_ALGO_NULL:\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,\n \t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CMAC_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n \tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n \t\t/* return maximum state1 size in this case */\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,\n@@ -1345,6 +1357,7 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n \tcase ICP_QAT_HW_AUTH_ALGO_MD5:\n \t\treturn ICP_QAT_HW_MD5_STATE1_SZ;\n \tcase ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:\n+\tcase ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC:\n \t\treturn ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;\n \tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n \t\t/* return maximum digest size in this case */\n@@ -2353,6 +2366,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC\n+\t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SM3\n@@ -2593,6 +2607,12 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t\treturn -EFAULT;\n \t\t}\n \t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC:\n+\t\tstate1_size = ICP_QAT_HW_AES_CMAC_STATE1_SZ;\n+\t\tmemset(cdesc->cd_cur_ptr, 0, state1_size);\n+\t\tmemcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);\n+\t\tstate2_size = ICP_QAT_HW_AES_128_CMAC_STATE2_SZ;\n+\t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n \t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;\n", "prefixes": [ "3/4" ] }