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GET /api/patches/135207/?format=api
{ "id": 135207, "url": "http://patches.dpdk.org/api/patches/135207/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231214151248.1654878-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231214151248.1654878-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231214151248.1654878-3-michaelba@nvidia.com", "date": "2023-12-14T15:12:48", "name": "[v3,2/2] net/mlx5: add random item support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7086589155d1adf82e61a15771513b099613b034", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231214151248.1654878-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 30558, "url": "http://patches.dpdk.org/api/series/30558/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30558", "date": "2023-12-14T15:12:47", "name": "net/mlx5: add random item support", "version": 3, "mbox": "http://patches.dpdk.org/series/30558/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135207/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/135207/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=RXC8SocXOcQhoDAqNySx0+JvT/nbb/Sy6DDAyX7UqNrUM6++zys0OJeq4fxswnfOHOhqO4cvc6p2LOoA+fKXPjBAKozDlmngvIMiYBw6Noe0cUndRAgz1tNK9HPSMnnVrTf2RvfT1Tn/Upj94tDeeMWMQGyH7NUcs0RXg4Xp7hZUmhJ6uH89ms8QTC62wBndeVrKJaF6jpR7WU4a/MFMrXA7R9LXEqEVz7jViILb6CGhWtDQYZaID7QFRYJks2HXKtQO6rJnv1XkqQmJR62hrPCZygxk6pT1xKH+1SqLF3w01dfI8XIsFQ9M9l1evEpLgknb/K7mCWmMfF8P3gNTxA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,\n Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v3 2/2] net/mlx5: add random item support", "Date": "Thu, 14 Dec 2023 17:12:48 +0200", "Message-ID": "<20231214151248.1654878-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231214151248.1654878-1-michaelba@nvidia.com>", "References": "<20231130164001.666702-1-michaelba@nvidia.com>\n <20231214151248.1654878-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB4B:EE_|PH7PR12MB5734:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8f7d7de6-63aa-494b-c33c-08dbfcb735e8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Hp4yWG2hi9xQTvYGZMweI7fxEKP9MWPLfUIycQsVsRckRorMQPXdEZKj/Ylfv4Br5Lnxa9OULoU/VAkOqgX11pUXZqKvNPrNDztDPL37AI5mXITLeG5cPE355jqErF+6vJBTy3AGLelMuTb32UHNZocMIJM74prn2NweZNza7FiJip2Ado1LeljO3VN1Rcw9Xx95f8KKYZed4uSFnpUjrvXl1nUTT1YKjA/dsUt2OR38SOZfWk+FnevizTKbRleF8fQvYrth3Gm4VeEboMJSLAhto28ic0nsXMqjQUmwwtU0oEJnUcAQXo4LENzfAdv6moduUJTtnf/OzS4p2RFbxice3LXI996HyamDODlm6MA7SAn3rNsI63x5ZoC+MwJVLHQA2blKNI9zKRhIwjYRSfi4Vdcwly4yTA+GxvvfLx9jMV5hxDYe0+U++8S1L0GQ55X436B82Vm4WPT7eGFmI3H3qPvCMJtMMhJlRtRIF7va787PD8NutERSbO7Guf1S0seX76i3KkpQb3aD1SBbIcVfIdFzD57ZnM8EvzamtHCa0ryPKdDiLt+Ub0S+HkLWhCP6lTwcBItwBagiIz6mqUVa4fB5aE2DH71s0apkZwLKYpMV+fSmIKBXAM39VOz1pE2C4ycnAZbtkGjulQoLvO1MGsrqyc8wdPShOv6bNYdFWmQUKi2h3M78Olv/uo0FMZzwVlOh/vnJSBL8DsDjmZBdTc7wrC+J/s2TcWLJ5kMZH4dFUsZJ9hxQcbvPRBqW", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(376002)(346002)(136003)(39860400002)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(82310400011)(36840700001)(40470700004)(46966006)(4326008)(8936002)(2906002)(316002)(83380400001)(36756003)(7636003)(40460700003)(82740400003)(8676002)(5660300002)(47076005)(36860700001)(7696005)(26005)(6286002)(336012)(41300700001)(2616005)(107886003)(478600001)(1076003)(6666004)(55016003)(54906003)(6916009)(356005)(70206006)(70586007)(86362001)(40480700001)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Dec 2023 15:13:21.4687 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8f7d7de6-63aa-494b-c33c-08dbfcb735e8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL6PEPF0001AB4B.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB5734", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for random item in HWS mode.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 9 +++++++++\n doc/guides/rel_notes/release_24_03.rst | 3 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 5 +++++\n drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++\n 5 files changed, 23 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex 0739fe9d63..6261b7d657 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -88,6 +88,7 @@ port_id = Y\n port_representor = Y\n ptype = Y\n quota = Y\n+random = Y\n tag = Y\n tcp = Y\n udp = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 6b52fb93c5..971c229850 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -167,6 +167,7 @@ Features\n - Sub-Function.\n - Matching on represented port.\n - Matching on aggregated affinity.\n+- Matching on random value.\n \n \n Limitations\n@@ -564,6 +565,7 @@ Limitations\n - Modification of the MPLS header is supported only in HWS and only to copy from,\n the encapsulation level is always 0.\n - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.\n+ - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.\n - Encapsulation levels are not supported, can modify outermost header fields only.\n - Offsets cannot skip past the boundary of a field.\n - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``\n@@ -770,6 +772,13 @@ Limitations\n - In HW steering (``dv_flow_en`` = 2):\n - not supported on guest port.\n \n+- Match on random value:\n+\n+ - Supported only with HW Steering enabled (``dv_flow_en`` = 2).\n+ - Supported only in table with ``nb_flows=1``.\n+ - NIC ingress/egress flow in group 0 is not supported.\n+ - Supports matching only 16 bits (LSB).\n+\n - During live migration to a new process set its flow engine as standby mode,\n the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).\n Live migration is only supported under SWS (``dv_flow_en=1``).\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 819cef7f20..93e58b55ca 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -60,6 +60,9 @@ New Features\n * Added ``RTE_FLOW_ITEM_TYPE_RANDOM`` to match random value.\n * Added ``RTE_FLOW_FIELD_RANDOM`` to represent it in field API.\n \n+* **Updated NVIDIA mlx5 net driver.**\n+\n+ * Added support for ``RTE_FLOW_ITEM_TYPE_RANDOM`` flow item.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 115d730317..67a44095d7 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -5396,6 +5396,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifications of the MPLS header \"\n \t\t\t\t\"is not supported\");\n+\tif (dst_data->field == RTE_FLOW_FIELD_RANDOM ||\n+\t src_data->field == RTE_FLOW_FIELD_RANDOM)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifications of random value is not supported\");\n \tif (dst_data->field == RTE_FLOW_FIELD_MARK ||\n \t src_data->field == RTE_FLOW_FIELD_MARK)\n \t\tif (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex da873ae2e2..af4e9abd89 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5047,6 +5047,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifying vlan_type is not supported\");\n+\tif (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifying random value is not supported\");\n \tif (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI))\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n@@ -6807,6 +6811,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n \t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\tcase RTE_FLOW_ITEM_TYPE_PTYPE:\n+\t\tcase RTE_FLOW_ITEM_TYPE_RANDOM:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "v3", "2/2" ] }