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GET /api/patches/135206/?format=api
{ "id": 135206, "url": "http://patches.dpdk.org/api/patches/135206/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231214151248.1654878-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231214151248.1654878-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231214151248.1654878-2-michaelba@nvidia.com", "date": "2023-12-14T15:12:47", "name": "[v3,1/2] net/mlx5/hws: add support for random number match", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e2b195deb3847c0fab839f9aaa376d095fa898a0", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231214151248.1654878-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 30558, "url": "http://patches.dpdk.org/api/series/30558/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30558", "date": "2023-12-14T15:12:47", "name": "net/mlx5: add random item support", "version": 3, "mbox": "http://patches.dpdk.org/series/30558/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135206/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/135206/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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<viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>, Erez Shitrit <erezsh@nvidia.com>", "Subject": "[PATCH v3 1/2] net/mlx5/hws: add support for random number match", "Date": "Thu, 14 Dec 2023 17:12:47 +0200", "Message-ID": "<20231214151248.1654878-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231214151248.1654878-1-michaelba@nvidia.com>", "References": "<20231130164001.666702-1-michaelba@nvidia.com>\n <20231214151248.1654878-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB4B:EE_|DS0PR12MB7679:EE_", "X-MS-Office365-Filtering-Correlation-Id": "feb3b6a5-d111-45bf-de25-08dbfcb7339b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", 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SFS:(13230031)(4636009)(346002)(136003)(396003)(376002)(39860400002)(230922051799003)(186009)(1800799012)(64100799003)(82310400011)(451199024)(36840700001)(46966006)(40470700004)(40460700003)(7636003)(356005)(47076005)(86362001)(40480700001)(8936002)(8676002)(2906002)(5660300002)(4326008)(82740400003)(107886003)(83380400001)(36860700001)(55016003)(426003)(316002)(26005)(1076003)(2616005)(6286002)(336012)(6916009)(54906003)(70206006)(70586007)(36756003)(41300700001)(7696005)(478600001)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Dec 2023 15:13:17.6093 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n feb3b6a5-d111-45bf-de25-08dbfcb7339b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL6PEPF0001AB4B.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB7679", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Erez Shitrit <erezsh@nvidia.com>\n\nThe HW adds a random number per each hash, this value can be used for\nstatistic calculation over the packets, for example by setting one bit in\nthe mask of that field we will get half of the traffic in the flow, and\nso on with the rest of the mask.\n\nSigned-off-by: Erez Shitrit <erezsh@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 33 +++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 8 ++++++-\n drivers/net/mlx5/mlx5_flow.h | 3 +++\n 3 files changed, 43 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 0b60479406..005733372a 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -182,6 +182,7 @@ struct mlx5dr_definer_conv_data {\n \tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \\\n \tX(SET,\t\tib_l4_udp_port,\t\tUDP_ROCEV2_PORT,\trte_flow_item_ib_bth) \\\n \tX(SET,\t\tib_l4_opcode,\t\tv->hdr.opcode,\t\trte_flow_item_ib_bth) \\\n+\tX(SET,\t\trandom_number,\t\tv->value,\t\trte_flow_item_random) \\\n \tX(SET,\t\tib_l4_bth_a,\t\tv->hdr.a,\t\trte_flow_item_ib_bth) \\\n \n /* Item set function format */\n@@ -2173,6 +2174,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\tstruct rte_flow_item *item,\n+\t\t\t\tint item_idx)\n+{\n+\tconst struct rte_flow_item_random *m = item->mask;\n+\tconst struct rte_flow_item_random *l = item->last;\n+\tstruct mlx5dr_definer_fc *fc;\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->value != (m->value & UINT16_MAX)) {\n+\t\tDR_LOG(ERR, \"Random value is 16 bits only\");\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];\n+\tfc->item_idx = item_idx;\n+\tfc->tag_set = &mlx5dr_definer_random_number_set;\n+\tfc->is_range = l && l->value;\n+\tDR_CALC_SET_HDR(fc, random_number, random_number);\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,\n \t\t\t struct mlx5dr_definer_fc *fc,\n@@ -2224,6 +2252,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)\n \tcase RTE_FLOW_ITEM_TYPE_TAG:\n \tcase RTE_FLOW_ITEM_TYPE_META:\n \tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n+\tcase RTE_FLOW_ITEM_TYPE_RANDOM:\n \t\treturn 0;\n \tdefault:\n \t\tDR_LOG(ERR, \"Range not supported over item type %d\", item->type);\n@@ -2537,6 +2566,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_ptype(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_PTYPE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_RANDOM:\n+\t\t\tret = mlx5dr_definer_conv_item_random(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_RANDOM;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex 6f1c99e37a..18591ef853 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -150,6 +150,7 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,\n \tMLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,\n \tMLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,\n+\tMLX5DR_DEFINER_FNAME_RANDOM_NUM,\n \tMLX5DR_DEFINER_FNAME_MAX,\n };\n \n@@ -407,6 +408,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {\n \tu8 destination_address[0x20];\n };\n \n+struct mlx5_ifc_definer_hl_random_number_bits {\n+\tu8 random_number[0x10];\n+\tu8 reserved[0x10];\n+};\n+\n struct mlx5_ifc_definer_hl_ipv6_addr_bits {\n \tu8 ipv6_address_127_96[0x20];\n \tu8 ipv6_address_95_64[0x20];\n@@ -516,7 +522,7 @@ struct mlx5_ifc_definer_hl_bits {\n \tstruct mlx5_ifc_definer_hl_mpls_bits mpls_inner;\n \tu8 unsupported_config_headers_outer[0x80];\n \tu8 unsupported_config_headers_inner[0x80];\n-\tu8 unsupported_random_number[0x20];\n+\tstruct mlx5_ifc_definer_hl_random_number_bits random_number;\n \tstruct mlx5_ifc_definer_hl_ipsec_bits ipsec;\n \tstruct mlx5_ifc_definer_hl_metadata_bits metadata;\n \tu8 unsupported_utc_timestamp[0x40];\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 6dde9de688..14311eff10 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -277,6 +277,9 @@ enum mlx5_feature_name {\n /* NSH ITEM */\n #define MLX5_FLOW_ITEM_NSH (1ull << 53)\n \n+/* Random ITEM */\n+#define MLX5_FLOW_ITEM_RANDOM (1ull << 53)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n", "prefixes": [ "v3", "1/2" ] }