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GET /api/patches/135176/?format=api
{ "id": 135176, "url": "http://patches.dpdk.org/api/patches/135176/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231214030428.363471-2-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231214030428.363471-2-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231214030428.363471-2-suanmingm@nvidia.com", "date": "2023-12-14T03:04:24", "name": "[1/4] net/mlx5: add TCP/IP length modify field", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c9add689f8887426bb5a3adc3666ecf22867ae5c", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231214030428.363471-2-suanmingm@nvidia.com/mbox/", "series": [ { "id": 30543, "url": "http://patches.dpdk.org/api/series/30543/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30543", "date": "2023-12-14T03:04:24", "name": "net/mlx5: add modify field ADD fields support", "version": 1, "mbox": "http://patches.dpdk.org/series/30543/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135176/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135176/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 04159436E9;\n\tThu, 14 Dec 2023 04:05:10 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9D46742F57;\n\tThu, 14 Dec 2023 04:05:10 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2041.outbound.protection.outlook.com [40.107.243.41])\n by mails.dpdk.org (Postfix) with ESMTP id E941140283\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Dariusz Sosnowski <dsosnowski@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Matan Azrad\n <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH 1/4] net/mlx5: add TCP/IP length modify field", "Date": "Thu, 14 Dec 2023 11:04:24 +0800", "Message-ID": "<20231214030428.363471-2-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231214030428.363471-1-suanmingm@nvidia.com>", "References": "<20231214030428.363471-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002BA4B:EE_|SN7PR12MB8148:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ccfaf790-6f7c-4653-0141-08dbfc517857", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n n645XRlUKAMjQiR/bBAGM4s/+I6PANROIwGHYPOmzMI/tk2G8g8/qAkBHkuteOm3uOotzfcBa+LE5zoHiEHM9hAJrDqWmqqMggH2CPtYXcaR6yPxdAcu36uOVrY+sKCua0BXX28UVN/cb6+91pEJ0VhaY+W+aQUlwEFA7nWbmHcT+yrDoTSbn9fPEoqkkTYKinNKUSl1XUNZEGa0sIL7BNv3aGL2bniKilHQA8UmMz6nRAQ+c4ej7YgDF8TJ3BmbVZS+nu0zbAVB0/Y5G0eskfK6fU6mdoShMbqtAYL8JqOs/2+hAZroXUI0ESeX+G1bsrTIPep6IqWdXGOTt/kVVwKcYl4uL4/Mjx9C4lTjv4NgACzs4XzvBCAdPA89acHRgOBQpNWdcV44MxpfKROVsgdW33szry5ouHqNpRp53cvWjickSSvHWyL5YXhWyKOAiURh9A9TcYWxRR1dNyKZtFoSvlLfGrakcS1JavRDYzGdkif5G1lNLuHjDcLBbInz+dhPQbBMNS80YBmh3XzMxaFt/tC7OJH1rc87yVxO8/dZ/cB7bnpS4x81c10WjrFSJE1ZKzYAGdHgJcgC2A1L8Y+ceYc0MRV0OPsGfZzk+wideZXTSWDhRWCjnJz6byaOH1cmr1phu8Q1UwGxCX0OOL9vbwmkvn9xFgNY22wcq0Qx8H8ETDOzgF0o7UKrfY7lMFZgm4enmJmgsXmnk5M6wRnzEzyhilR9gC29rDV7rSoulWzYAXNy7gfNKh3yoebP", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(136003)(39860400002)(346002)(376002)(230922051799003)(82310400011)(64100799003)(451199024)(1800799012)(186009)(40470700004)(46966006)(36840700001)(86362001)(36756003)(40480700001)(40460700003)(55016003)(6666004)(70206006)(70586007)(110136005)(7696005)(41300700001)(82740400003)(1076003)(356005)(16526019)(107886003)(336012)(26005)(6286002)(426003)(7636003)(83380400001)(47076005)(5660300002)(54906003)(2906002)(8676002)(478600001)(4326008)(36860700001)(8936002)(6636002)(316002)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Dec 2023 03:05:04.3169 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ccfaf790-6f7c-4653-0141-08dbfc517857", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002BA4B.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB8148", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit adds TCP data offset, IPv4 total length, IPv4 IHL,\nIPv6 payload length in modify field operation.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 4 ++++\n drivers/net/mlx5/mlx5_flow_dv.c | 40 +++++++++++++++++++++++++++++++++\n 2 files changed, 44 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 9e22dce6da..0d46ba9c40 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -848,6 +848,10 @@ enum mlx5_modification_field {\n \tMLX5_MODI_META_REG_C_13 = 0x94,\n \tMLX5_MODI_META_REG_C_14 = 0x95,\n \tMLX5_MODI_META_REG_C_15 = 0x96,\n+\tMLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D,\n+\tMLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E,\n+\tMLX5_MODI_OUT_IPV4_IHL = 0x11F,\n+\tMLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120,\n \tMLX5_MODI_INVALID = INT_MAX,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 115d730317..4e2095dcfe 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1664,6 +1664,16 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_IPV4_IHL:\n+\t\tMLX5_ASSERT(data->offset + width <= 4);\n+\t\toff_be = 4 - (data->offset + width);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0,\n+\t\t\t\t\tMLX5_MODI_OUT_IPV4_IHL};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_IPV4_DSCP:\n \t\tMLX5_ASSERT(data->offset + width <= 6);\n \t\toff_be = 6 - (data->offset + width);\n@@ -1674,6 +1684,16 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_IPV4_TOTAL_LEN:\n+\t\tMLX5_ASSERT(data->offset + width <= 16);\n+\t\toff_be = 16 - (data->offset + width);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0,\n+\t\t\t\t\tMLX5_MODI_OUT_IPV4_TOTAL_LEN};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_IPV4_TTL:\n \t\tMLX5_ASSERT(data->offset + width <= 8);\n \t\toff_be = 8 - (data->offset + width);\n@@ -1714,6 +1734,16 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:\n+\t\tMLX5_ASSERT(data->offset + width <= 16);\n+\t\toff_be = 16 - (data->offset + width);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0,\n+\t\t\t\t\tMLX5_MODI_OUT_IPV6_PAYLOAD_LEN};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_IPV6_HOPLIMIT:\n \t\tMLX5_ASSERT(data->offset + width <= 8);\n \t\toff_be = 8 - (data->offset + width);\n@@ -1860,6 +1890,16 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_TCP_DATA_OFFSET:\n+\t\tMLX5_ASSERT(data->offset + width <= 4);\n+\t\toff_be = 4 - (data->offset + width);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0,\n+\t\t\t\t\tMLX5_MODI_OUT_TCP_DATA_OFFSET};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_UDP_PORT_SRC:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n", "prefixes": [ "1/4" ] }