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GET /api/patches/134766/?format=api
{ "id": 134766, "url": "http://patches.dpdk.org/api/patches/134766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-22-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231203112543.844014-22-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231203112543.844014-22-michaelba@nvidia.com", "date": "2023-12-03T11:25:41", "name": "[v1,21/23] net/mlx5: add GENEVE option support for group 0", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3f69c3ce08a83206adf153df15c885d5315655bc", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-22-michaelba@nvidia.com/mbox/", "series": [ { "id": 30433, "url": "http://patches.dpdk.org/api/series/30433/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30433", "date": "2023-12-03T11:25:23", "name": "net/mlx5: support Geneve and options for HWS", "version": 1, "mbox": "http://patches.dpdk.org/series/30433/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134766/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/134766/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 939174365F;\n\tSun, 3 Dec 2023 12:28:41 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7207B4069D;\n\tSun, 3 Dec 2023 12:27:01 +0100 (CET)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2051.outbound.protection.outlook.com [40.107.244.51])\n by mails.dpdk.org (Postfix) with ESMTP id 643A340648\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v1 21/23] net/mlx5: add GENEVE option support for group 0", "Date": "Sun, 3 Dec 2023 13:25:41 +0200", "Message-ID": "<20231203112543.844014-22-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231203112543.844014-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000042A8:EE_|PH7PR12MB8596:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0e50d837-e835-4e62-cfd3-08dbf3f2c240", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +jhqz3Zc586XjpQGPPHo/m9A9hYJ6dCst1i3KdBCnGnkRE12E87awHoFk2LiRViYzzpsef3i6gpI5lWCHcPEkzhJ/yrJjGNiwFeGq3vekgjDP4YbKsdZLlgKdivJJI/Qyd5cSOhsns4xPH/zN79MPjfx1mDk6FVOeqO/MVjbNg6Z50mS1S3OVxFqIkVXE6NHbpBZmx7GmyYr/XxEFHYfQhrLrH2DdnG7HXG3oMKEJwwVtL9g4WJMEUZMRMnY37o3LPQJN0OKfhrdCt8bkiwOruoeODp++OOLSn2LJOcCEbePbVgAElm8pYLYpAZgI2lyr3KKm4vK7TosAmkBRPu1Uy2AHNecBEO9jJHqWEtNkp4/kmyGKcV6V6VyM2AQQjDHqJ01rpVUW0ck6NxiBqqpuQ6Z4jYJXQdSriKV7Kpfr2XZ9s1/gV1+okkv8XfCxjxxgPd1LfpkiSJ/FUHpRQ7zz5PLpiUpDAvs8fowyTd9I4SxCAF+oKPPxz80mBXBqrcgkWsqjK+/jgM4Dq2fmjzG8hy/sCvUirw3vfB60zXSOHZasJGU7XQGDNsd59UcjjbuE4uLs++D3rcF7xJUbl8Gb95T5moIxt7A6V/RvnFM+AaTpiFuqWrWoVpobDds5/TKwZBn313ecd3k3eMvpsXTVK0nA2tezSnYsKUZb7Ejxne+suTL9XopZH8JR0TQd+9WR09tFsDPCY/ztIe/AQkly8H3QOo3+Z2ZHA1Oho1gEO4CtRcXo6LZOI4o66D+aSR+", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(376002)(396003)(39860400002)(136003)(230922051799003)(64100799003)(1800799012)(186009)(82310400011)(451199024)(36840700001)(40470700004)(46966006)(40480700001)(55016003)(40460700003)(36860700001)(356005)(47076005)(7636003)(2906002)(5660300002)(82740400003)(83380400001)(336012)(426003)(1076003)(7696005)(107886003)(6666004)(2616005)(26005)(6286002)(478600001)(36756003)(41300700001)(70206006)(54906003)(6916009)(316002)(4326008)(8676002)(8936002)(70586007)(86362001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Dec 2023 11:26:56.8157 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0e50d837-e835-4e62-cfd3-08dbf3f2c240", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000042A8.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB8596", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for HWS GENEVE options for flex parser profile 0 and group\n0.\n\nThis patch avoids parser creation during matcher/flow preparation for HW\nsteering (MLX5_SET_MATCHER_HS) and removes some logic done in\n\"flow_dev_geneve_tlv_option_resource_*()\" functions when dv_flow_en=2.\n\nAfter this change, those functions became static and they were removed\nfrom header file.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 8 +-------\n drivers/net/mlx5/mlx5_flow.h | 4 ----\n drivers/net/mlx5/mlx5_flow_dv.c | 24 +++++++++++-------------\n 3 files changed, 12 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 5f8af31aea..881c42a97a 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2049,13 +2049,7 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)\n \t} while (++i <= sh->bond.n_port);\n \tif (sh->td)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(sh->td));\n-#ifdef HAVE_MLX5_HWS_SUPPORT\n-\t/* HWS manages geneve_tlv_option resource as global. */\n-\tif (sh->config.dv_flow_en == 2)\n-\t\tflow_dev_geneve_tlv_option_resource_release(sh);\n-\telse\n-#endif\n-\t\tMLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);\n+\tMLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);\n \tpthread_mutex_destroy(&sh->txpp.mutex);\n \tmlx5_lwm_unset(sh);\n \tmlx5_physical_device_destroy(sh->phdev);\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 04a2eb0b0c..808f364c6c 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2825,10 +2825,6 @@ void flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);\n \n struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,\n \t\t\t\t\t\t uint32_t age_idx);\n-int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n-\t\t\t\t\t const struct rte_flow_item *item,\n-\t\t\t\t\t struct rte_flow_error *error);\n-void flow_dev_geneve_tlv_option_resource_release(struct mlx5_dev_ctx_shared *sh);\n \n void flow_release_workspace(void *data);\n int mlx5_flow_os_init_workspace_once(void);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 8894f51f4c..72e0d82e7b 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9880,7 +9880,7 @@ flow_dv_translate_item_geneve(void *key, const struct rte_flow_item *item,\n /**\n * Create Geneve TLV option resource.\n *\n- * @param dev[in, out]\n+ * @param[in, out] dev\n * Pointer to rte_eth_dev structure.\n * @param[in] item\n * Flow pattern to translate.\n@@ -9890,8 +9890,7 @@ flow_dv_translate_item_geneve(void *key, const struct rte_flow_item *item,\n * @return\n * 0 on success otherwise -errno and errno is set.\n */\n-\n-int\n+static int\n flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n \t\t\t\t\t const struct rte_flow_item *item,\n \t\t\t\t\t struct rte_flow_error *error)\n@@ -9904,6 +9903,7 @@ flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n \tconst struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;\n \tint ret = 0;\n \n+\tMLX5_ASSERT(sh->config.dv_flow_en == 1);\n \tif (!geneve_opt_v)\n \t\treturn -1;\n \trte_spinlock_lock(&sh->geneve_tlv_opt_sl);\n@@ -9914,13 +9914,8 @@ flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n \t\t\tgeneve_opt_v->option_type &&\n \t\t\tgeneve_opt_resource->length ==\n \t\t\tgeneve_opt_v->option_len) {\n-\t\t\t/*\n-\t\t\t * We already have GENEVE TLV option obj allocated.\n-\t\t\t * Increasing refcnt only in SWS. HWS uses it as global.\n-\t\t\t */\n-\t\t\tif (priv->sh->config.dv_flow_en == 1)\n-\t\t\t\t__atomic_fetch_add(&geneve_opt_resource->refcnt, 1,\n-\t\t\t\t\t\t __ATOMIC_RELAXED);\n+\t\t\t__atomic_fetch_add(&geneve_opt_resource->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t} else {\n \t\t\tret = rte_flow_error_set(error, ENOMEM,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n@@ -9999,8 +9994,11 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key,\n \t\treturn -1;\n \tMLX5_ITEM_UPDATE(item, key_type, geneve_opt_v, geneve_opt_m,\n \t\t\t &rte_flow_item_geneve_opt_mask);\n-\t/* Register resource requires item spec. */\n-\tif (key_type & MLX5_SET_MATCHER_V) {\n+\t/*\n+\t * Register resource requires item spec for SW steering,\n+\t * for HW steering resources is registered explicitly by user.\n+\t */\n+\tif (key_type & MLX5_SET_MATCHER_SW_V) {\n \t\tret = flow_dev_geneve_tlv_option_resource_register(dev, item,\n \t\t\t\t\t\t\t\t error);\n \t\tif (ret) {\n@@ -15777,7 +15775,7 @@ flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,\n \t\t\t\t &resource->entry);\n }\n \n-void\n+static void\n flow_dev_geneve_tlv_option_resource_release(struct mlx5_dev_ctx_shared *sh)\n {\n \tstruct mlx5_geneve_tlv_option_resource *geneve_opt_resource =\n", "prefixes": [ "v1", "21/23" ] }