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GET /api/patches/134758/?format=api
http://patches.dpdk.org/api/patches/134758/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-12-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231203112543.844014-12-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231203112543.844014-12-michaelba@nvidia.com", "date": "2023-12-03T11:25:31", "name": "[v1,11/23] common/mlx5: add function to query GENEVE TLV option", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ee80a6cc9cdd47b68ac51ab3a4ad1838116360f2", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-12-michaelba@nvidia.com/mbox/", "series": [ { "id": 30433, "url": "http://patches.dpdk.org/api/series/30433/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30433", "date": "2023-12-03T11:25:23", "name": "net/mlx5: support Geneve and options for HWS", "version": 1, "mbox": "http://patches.dpdk.org/series/30433/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134758/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/134758/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=Wumsgh9iSkOPY3PuwT840u7EFlr2rJ8g2QGlMOGmw+ZnFN2LPaG4s+VBa1FH5k7tJCFLG1wir23v82MaB/5LJTYxWBK76qXzdAg1YbwUmlae0723YS3ieUC+c4jBUCZIYEjFgAz/A4jw1zEUUanEXUynTGncD5FI3dGSFtIgsFC9wQUF9trvBWz63r3TndVUX+H1QFkUQm4C6lr/hdcwF4wURlBBEMvR+4NrKhDZ49WDcTjdMHvMm7mP7z1fC7QsdWn17Ayreb151FwmEL6rvoCsXZEMNtDXHnnoGZgFNPp5ERqFP/31LPw0tazgd+av7x9ofNQPLV0LeZ6GX/xiDg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v1 11/23] common/mlx5: add function to query GENEVE TLV option", "Date": "Sun, 3 Dec 2023 13:25:31 +0200", "Message-ID": "<20231203112543.844014-12-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231203112543.844014-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000042AB:EE_|BN9PR12MB5052:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a8453175-65ee-4d32-e76e-08dbf3f2b3df", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 3WV3zLDMp7Pwfq6chtPHLn+8C1uPaRoWgKni7PxTjmtJMJ2kLqdo0vZ+KkTBUjeIFxXkryYORZpjihHh/3j5zJPvFRl9Jea5Yb3XIx4D3QqxbTn62o1HizT0pkYmEaaBG7mkvs7aTIonVH8IBMXPub3oi0emHMRQ/FzTS1RxruEUDRMBLyQazojPQaWEez9XCMxyIILPqz/yWk6siTLmFJGYtoU+BD/gr8zFXj8vznMxZr04Gkwk7y+7R3jHsMLH2bQrNdVe0qGVWmNcls6UgvgWQnhu89pNRcqMedsEo9BoZfIBKNWPI/Z9zCk0u/HfW+wLTKH6X3d4yIpKpV/CNwrF3LxWh9MhubyQfwW+M1chaag5kH/PjciqWxFUy7UZlfOgpf/TatGEupL910xn3Y5WrY9FBGAdrsY4t3XmBqhu/EcVbwaxJp7K0Q2GOP+/DLc8dq3bAoPLKL65Dt6noetoJgBk7gxiYJ7sTu2su3xY2cc47xqroQAFES/iLGdH1VRGeP0YzOChHDWAwQwjBWxvPgSnShAV/hjkxZW77b+qCoNxDcpgRngIvNl3safxf8epYvgy8dZoR+6YMpBLbrHwArVKbpv1eB2CxeFwBj2paeMtbG8cmSRD3t1mzgthKozQ/GPyHGqidZTz+EEAK0Z+waq7vTZ4QzyZYzCTkYBsyKEDgztlV11XiapGJHg9tJCNhxjVuI5ElVEfg6ZRWd0GE0l0Rg9CDhsgCx0104dq3arkKPWDZyQR07rl1mDL", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(230922051799003)(186009)(451199024)(1800799012)(82310400011)(64100799003)(36840700001)(46966006)(40470700004)(1076003)(426003)(336012)(6286002)(26005)(55016003)(82740400003)(6666004)(478600001)(107886003)(2616005)(7696005)(40480700001)(8936002)(70206006)(70586007)(6916009)(54906003)(4326008)(316002)(8676002)(36860700001)(356005)(7636003)(47076005)(41300700001)(40460700003)(2906002)(5660300002)(86362001)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Dec 2023 11:26:32.6925 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a8453175-65ee-4d32-e76e-08dbf3f2b3df", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000042AB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR12MB5052", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add a new function to query information about GENEVE TLV option parser.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 50 ++++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 6 ++++\n drivers/common/mlx5/mlx5_prm.h | 5 +++\n drivers/common/mlx5/version.map | 1 +\n 4 files changed, 62 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 332aebbe57..1fa75cd964 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2915,6 +2915,56 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n \treturn geneve_tlv_opt_obj;\n }\n \n+/**\n+ * Query GENEVE TLV option using DevX API.\n+ *\n+ * @param[in] ctx\n+ * Context used to create GENEVE TLV option object.\n+ * @param[in] geneve_tlv_opt_obj\n+ * DevX object of the GENEVE TLV option.\n+ * @param[out] attr\n+ * Pointer to match sample info attributes structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,\n+\t\t\t\t struct mlx5_devx_obj *geneve_tlv_opt_obj,\n+\t\t\t\t struct mlx5_devx_match_sample_info_query_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};\n+\tvoid *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);\n+\tvoid *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,\n+\t\t\t\t geneve_tlv_opt);\n+\tint ret;\n+\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_QUERY_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);\n+\t/* Call first query to get sample handle. */\n+\tret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),\n+\t\t\t\t\tout, sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to query GENEVE TLV option using DevX.\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\t/* Call second query to get sample information. */\n+\tif (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {\n+\t\tuint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,\n+\t\t\t\t\t geneve_sample_field_id);\n+\n+\t\treturn mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,\n+\t\t\t\t\t\t\t attr);\n+\t}\n+\tDRV_LOG(DEBUG, \"GENEVE TLV option sample isn't valid.\");\n+\treturn 0;\n+}\n+\n int\n mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)\n {\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 1daf2fcca4..6161c275da 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -794,6 +794,12 @@ struct mlx5_devx_obj *\n mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n \t\t\t\t struct mlx5_devx_geneve_tlv_option_attr *attr);\n \n+__rte_internal\n+int\n+mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,\n+\t\t\t\t struct mlx5_devx_obj *geneve_tlv_opt_obj,\n+\t\t\t\t struct mlx5_devx_match_sample_info_query_attr *attr);\n+\n /**\n * Create virtio queue counters object DevX API.\n *\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 59643a8788..7c36961564 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3721,6 +3721,11 @@ struct mlx5_ifc_create_geneve_tlv_option_in_bits {\n \tstruct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;\n };\n \n+struct mlx5_ifc_query_geneve_tlv_option_out_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;\n+};\n+\n struct mlx5_ifc_create_rtc_in_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_rtc_bits rtc;\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex 074eed46fd..589a450145 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -54,6 +54,7 @@ INTERNAL {\n \tmlx5_devx_cmd_modify_tir;\n \tmlx5_devx_cmd_modify_virtq;\n \tmlx5_devx_cmd_qp_query_tis_td;\n+\tmlx5_devx_cmd_query_geneve_tlv_option;\n \tmlx5_devx_cmd_query_hca_attr;\n \tmlx5_devx_cmd_query_lag;\n \tmlx5_devx_cmd_query_parse_samples;\n", "prefixes": [ "v1", "11/23" ] }{ "id": 134758, "url": "