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GET /api/patches/134751/?format=api
{ "id": 134751, "url": "http://patches.dpdk.org/api/patches/134751/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-9-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231203112543.844014-9-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231203112543.844014-9-michaelba@nvidia.com", "date": "2023-12-03T11:25:28", "name": "[v1,08/23] common/mlx5: add PRM attribute for TLV sample", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6468c5a1bb9f8bf3911c4d60e3ea27c0c4badb4c", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-9-michaelba@nvidia.com/mbox/", "series": [ { "id": 30433, "url": "http://patches.dpdk.org/api/series/30433/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30433", "date": "2023-12-03T11:25:23", "name": "net/mlx5: support Geneve and options for HWS", "version": 1, "mbox": "http://patches.dpdk.org/series/30433/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134751/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/134751/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 216F44365F;\n\tSun, 3 Dec 2023 12:26:55 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3DAD24067D;\n\tSun, 3 Dec 2023 12:26:25 +0100 (CET)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1nam02on2076.outbound.protection.outlook.com [40.107.96.76])\n by mails.dpdk.org (Postfix) with ESMTP id 4013440648\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v1 08/23] common/mlx5: add PRM attribute for TLV sample", "Date": "Sun, 3 Dec 2023 13:25:28 +0200", "Message-ID": "<20231203112543.844014-9-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231203112543.844014-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF00017097:EE_|CYYPR12MB8731:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9d582ca6-f92d-4e3d-b131-08dbf3f2aa87", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /Y/v4ufscisvYjWVbaJeMcH88bWIYcCtnHW+phKwQEjErbTA3h+KC/ldxfKzJ5vPKz46kakbLB/o0+JNzRc81wrwObN/tMSuR6BLCGq8/3T30T+a6UCslCQQ/ZI7fhwqjJYdHuAlBILF14KkAUXPJtmr5xvQpCiLVn7HGo4kzAGjQ27l4wCzLmKTBTyisjzFQWI1siJ1AK9UVF6zaOolKXkmQiCnKjh1W/acXUs1PzGZ685Fa8Iw6ncwilDShX/0du6OOXsJ8NHIz0aOyKZFQCBqoJpx6dtARAhmqSSTIr7QQd0LDR/u74+twor+2SHFyWDm7MrnHURJWBV7WLaIKFDLa7dpbd0q1ZSJP4wRHKVXzD1DU6jP/PDtRNnlxN9byDItp30MvGnqksFdCe6k+AKxGdfb1dfOvt7LXdmKIh5DtFK5B4s/oiyK7oFngughlyonCIiOa0V0pSVOth9K1UbjTqgEQJbPzPfneVdFtYlq3nQjMceHc6ZL+opsAAey/TdrL9Qa2/b+XQUNlf+73b7p1/k9O1QAluv4AUx00ySypzoR6H3Ig5mmQbNDIBMRdeqrjOO2GiGWTLlf9G1weDe+awfP+I0yt4yM6AwlqEWrIs/HgPpjeDbkXFjD8RmHp9D1z+debFrooCW5+mzZRCIgG2ypNmoP7HJrsX69K8TSOlReqeeAWBmowpxN2OAzkt91FkG4JR9ZlNlI+MFIhiNhqDmV0eT2trFS4XZEAW4r4Mw68ESHEoZ8cUJeGkay", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(376002)(39860400002)(396003)(136003)(230922051799003)(82310400011)(1800799012)(64100799003)(186009)(451199024)(46966006)(40470700004)(36840700001)(478600001)(26005)(83380400001)(7636003)(336012)(6286002)(47076005)(6666004)(7696005)(356005)(1076003)(40480700001)(82740400003)(426003)(36756003)(107886003)(2616005)(316002)(6916009)(54906003)(70206006)(70586007)(36860700001)(55016003)(5660300002)(4326008)(86362001)(2906002)(8936002)(8676002)(40460700003)(41300700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Dec 2023 11:26:17.0149 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9d582ca6-f92d-4e3d-b131-08dbf3f2aa87", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF00017097.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CYYPR12MB8731", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add GENEVE TLV sample fields in 2 places:\n1. New HCA capabilities indicating GENEVE TLV sample is supported.\n2. New fields in \"mlx5_ifc_geneve_tlv_option_bits\" structure.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 18 ++++++++++++++++--\n drivers/common/mlx5/mlx5_devx_cmds.h | 9 +++++++--\n drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++----\n 3 files changed, 34 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 9855a97bf4..674130c11f 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -968,6 +968,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\tmax_geneve_tlv_options);\n \tattr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\tmax_geneve_tlv_option_data_len);\n+\tattr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t geneve_tlv_option_offset);\n+\tattr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t geneve_tlv_sample);\n \tattr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t query_match_sample_info);\n \tattr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);\n@@ -2883,11 +2887,21 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n \t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n \tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n \t\t MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);\n-\tMLX5_SET(geneve_tlv_option, opt, option_class,\n-\t\t rte_be_to_cpu_16(attr->option_class));\n \tMLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);\n \tMLX5_SET(geneve_tlv_option, opt, option_data_length,\n \t\t attr->option_data_len);\n+\tif (attr->option_class_ignore)\n+\t\tMLX5_SET(geneve_tlv_option, opt, option_class_ignore,\n+\t\t\t attr->option_class_ignore);\n+\telse\n+\t\tMLX5_SET(geneve_tlv_option, opt, option_class,\n+\t\t\t rte_be_to_cpu_16(attr->option_class));\n+\tif (attr->offset_valid) {\n+\t\tMLX5_SET(geneve_tlv_option, opt, sample_offset_valid,\n+\t\t\t attr->offset_valid);\n+\t\tMLX5_SET(geneve_tlv_option, opt, sample_offset,\n+\t\t\t attr->sample_offset);\n+\t}\n \tgeneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,\n \t\t\t\t\t\t\t sizeof(in), out,\n \t\t\t\t\t\t\t sizeof(out));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 78337dff17..3f294e8f04 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -212,8 +212,10 @@ struct mlx5_hca_attr {\n \tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n \tuint16_t lro_min_mss_size;\n \tuint32_t flex_parser_protocols;\n-\tuint32_t max_geneve_tlv_options;\n-\tuint32_t max_geneve_tlv_option_data_len;\n+\tuint32_t max_geneve_tlv_options:8;\n+\tuint32_t max_geneve_tlv_option_data_len:5;\n+\tuint32_t geneve_tlv_sample:1;\n+\tuint32_t geneve_tlv_option_offset:1;\n \tuint32_t hairpin:1;\n \tuint32_t log_max_hairpin_queues:5;\n \tuint32_t log_max_hairpin_wq_data_sz:5;\n@@ -674,6 +676,9 @@ struct mlx5_devx_geneve_tlv_option_attr {\n \tuint32_t option_class:16;\n \tuint32_t option_type:8;\n \tuint32_t option_data_len:5;\n+\tuint32_t option_class_ignore:1;\n+\tuint32_t offset_valid:1;\n+\tuint32_t sample_offset:8;\n };\n \n /* mlx5_devx_cmds.c */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 9e22dce6da..59643a8788 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1849,7 +1849,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 num_of_uars_per_page[0x20];\n \tu8 flex_parser_protocols[0x20];\n \tu8 max_geneve_tlv_options[0x8];\n-\tu8 reserved_at_568[0x3];\n+\tu8 geneve_tlv_sample[0x1];\n+\tu8 geneve_tlv_option_offset[0x1];\n+\tu8 reserved_at_56a[0x1];\n \tu8 max_geneve_tlv_option_data_len[0x5];\n \tu8 flex_parser_header_modify[0x1];\n \tu8 reserved_at_571[0x2];\n@@ -3416,16 +3418,21 @@ struct mlx5_ifc_virtio_q_counters_bits {\n \n struct mlx5_ifc_geneve_tlv_option_bits {\n \tu8 modify_field_select[0x40];\n-\tu8 reserved_at_40[0x18];\n+\tu8 reserved_at_40[0x8];\n+\tu8 sample_offset[0x8];\n+\tu8 sample_id_valid[0x1];\n+\tu8 sample_offset_valid[0x1];\n+\tu8 option_class_ignore[0x1];\n+\tu8 reserved_at_53[0x5];\n \tu8 geneve_option_fte_index[0x8];\n \tu8 option_class[0x10];\n \tu8 option_type[0x8];\n \tu8 reserved_at_78[0x3];\n \tu8 option_data_length[0x5];\n-\tu8 reserved_at_80[0x180];\n+\tu8 geneve_sample_field_id[0x20];\n+\tu8 reserved_at_a0[0x160];\n };\n \n-\n enum mlx5_ifc_rtc_update_mode {\n \tMLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0,\n \tMLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1,\n", "prefixes": [ "v1", "08/23" ] }