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GET /api/patches/134012/?format=api
{ "id": 134012, "url": "http://patches.dpdk.org/api/patches/134012/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231109085547.1313003-3-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231109085547.1313003-3-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231109085547.1313003-3-suanmingm@nvidia.com", "date": "2023-11-09T08:55:47", "name": "[2/2] net/mlx5: fix destroying external representor matched flows", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "125a19523e50f949a275b358a25ef7cf783b98fc", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231109085547.1313003-3-suanmingm@nvidia.com/mbox/", "series": [ { "id": 30213, "url": "http://patches.dpdk.org/api/series/30213/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30213", "date": "2023-11-09T08:55:45", "name": "net/mlx5: fix flow rules for external SQ", "version": 1, "mbox": "http://patches.dpdk.org/series/30213/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/134012/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/134012/checks/", "tags": {}, "related": [], "headers": { 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"Subject": "[PATCH 2/2] net/mlx5: fix destroying external representor matched\n flows", "Date": "Thu, 9 Nov 2023 16:55:47 +0800", "Message-ID": "<20231109085547.1313003-3-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231109085547.1313003-1-suanmingm@nvidia.com>", "References": "<20231109085547.1313003-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF0000343E:EE_|LV3PR12MB9144:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3084ca0b-7d99-45ff-dcab-08dbe101c284", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230031)(4636009)(396003)(376002)(39860400002)(136003)(346002)(230273577357003)(230922051799003)(230173577357003)(64100799003)(451199024)(1800799009)(186009)(82310400011)(40470700004)(36840700001)(46966006)(5660300002)(41300700001)(36860700001)(40460700003)(2906002)(86362001)(36756003)(7636003)(356005)(82740400003)(336012)(16526019)(426003)(478600001)(83380400001)(70206006)(6286002)(110136005)(2616005)(70586007)(1076003)(26005)(6636002)(54906003)(316002)(47076005)(7696005)(6666004)(8676002)(4326008)(40480700001)(8936002)(55016003)(450100002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Nov 2023 08:56:27.6354 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3084ca0b-7d99-45ff-dcab-08dbe101c284", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF0000343E.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV3PR12MB9144", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The external representor matched SQ flows are managed by external\nSQ, PMD traffic enable/disable should not touch these flows.\n\nThis commit adds an extra external list for the external representor\nmatched SQ flows.\n\nFixes: 26e1eaf2dac4 (\"net/mlx5: support device control for E-Switch default rule\")\n\nCc: stable@dpdk.org\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow.h | 4 +--\n drivers/net/mlx5/mlx5_flow_hw.c | 45 +++++++++++++++++++++++----------\n drivers/net/mlx5/mlx5_trigger.c | 4 +--\n drivers/net/mlx5/mlx5_txq.c | 4 +--\n 5 files changed, 39 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 45ad0701f1..795748eddc 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1855,6 +1855,7 @@ struct mlx5_priv {\n \tvoid *root_drop_action; /* Pointer to root drop action. */\n \trte_spinlock_t hw_ctrl_lock;\n \tLIST_HEAD(hw_ctrl_flow, mlx5_hw_ctrl_flow) hw_ctrl_flows;\n+\tLIST_HEAD(hw_ext_ctrl_flow, mlx5_hw_ctrl_flow) hw_ext_ctrl_flows;\n \tstruct rte_flow_template_table *hw_esw_sq_miss_root_tbl;\n \tstruct rte_flow_template_table *hw_esw_sq_miss_tbl;\n \tstruct rte_flow_template_table *hw_esw_zero_tbl;\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex d57b3b5465..8c0b9a4b60 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2874,12 +2874,12 @@ int flow_null_counter_query(struct rte_eth_dev *dev,\n int mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *dev);\n \n int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint32_t sqn);\n+\t\t\t\t\t uint32_t sqn, bool external);\n int mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev,\n \t\t\t\t\t uint32_t sqn);\n int mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev);\n int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev);\n-int mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn);\n+int mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external);\n int mlx5_flow_actions_validate(struct rte_eth_dev *dev,\n \t\tconst struct rte_flow_actions_template_attr *attr,\n \t\tconst struct rte_flow_action actions[],\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex d512889682..8a23c7c281 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -9189,6 +9189,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \tpriv->nb_queue = nb_q_updated;\n \trte_spinlock_init(&priv->hw_ctrl_lock);\n \tLIST_INIT(&priv->hw_ctrl_flows);\n+\tLIST_INIT(&priv->hw_ext_ctrl_flows);\n \tret = flow_hw_create_ctrl_rx_tables(dev);\n \tif (ret) {\n \t\trte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n@@ -11343,6 +11344,8 @@ const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {\n * Index of an action template associated with @p table.\n * @param info\n * Additional info about control flow rule.\n+ * @param external\n+ * External ctrl flow.\n *\n * @return\n * 0 on success, negative errno value otherwise and rte_errno set.\n@@ -11355,7 +11358,8 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,\n \t\t\t uint8_t item_template_idx,\n \t\t\t struct rte_flow_action actions[],\n \t\t\t uint8_t action_template_idx,\n-\t\t\t struct mlx5_hw_ctrl_flow_info *info)\n+\t\t\t struct mlx5_hw_ctrl_flow_info *info,\n+\t\t\t bool external)\n {\n \tstruct mlx5_priv *priv = proxy_dev->data->dev_private;\n \tuint32_t queue = CTRL_QUEUE_ID(priv);\n@@ -11406,7 +11410,10 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,\n \t\tentry->info = *info;\n \telse\n \t\tentry->info.type = MLX5_HW_CTRL_FLOW_TYPE_GENERAL;\n-\tLIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);\n+\tif (external)\n+\t\tLIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);\n+\telse\n+\t\tLIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);\n \trte_spinlock_unlock(&priv->hw_ctrl_lock);\n \treturn 0;\n error:\n@@ -11580,11 +11587,23 @@ flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)\n \t\tmlx5_free(cf);\n \t\tcf = cf_next;\n \t}\n+\tcf = LIST_FIRST(&priv->hw_ext_ctrl_flows);\n+\twhile (cf != NULL) {\n+\t\tcf_next = LIST_NEXT(cf, next);\n+\t\tret = flow_hw_destroy_ctrl_flow(dev, cf->flow);\n+\t\tif (ret) {\n+\t\t\trte_errno = ret;\n+\t\t\treturn -ret;\n+\t\t}\n+\t\tLIST_REMOVE(cf, next);\n+\t\tmlx5_free(cf);\n+\t\tcf = cf_next;\n+\t}\n \treturn 0;\n }\n \n int\n-mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n+mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)\n {\n \tuint16_t port_id = dev->data->port_id;\n \tstruct rte_flow_item_ethdev esw_mgr_spec = {\n@@ -11668,7 +11687,7 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t\t.type = RTE_FLOW_ACTION_TYPE_END,\n \t};\n \tret = flow_hw_create_ctrl_flow(dev, proxy_dev, proxy_priv->hw_esw_sq_miss_root_tbl,\n-\t\t\t\t items, 0, actions, 0, &flow_info);\n+\t\t\t\t items, 0, actions, 0, &flow_info, external);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u failed to create root SQ miss flow rule for SQ %u, ret %d\",\n \t\t\tport_id, sqn, ret);\n@@ -11699,7 +11718,7 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t};\n \tflow_info.type = MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS;\n \tret = flow_hw_create_ctrl_flow(dev, proxy_dev, proxy_priv->hw_esw_sq_miss_tbl,\n-\t\t\t\t items, 0, actions, 0, &flow_info);\n+\t\t\t\t items, 0, actions, 0, &flow_info, external);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d\",\n \t\t\tport_id, sqn, ret);\n@@ -11821,7 +11840,7 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)\n \t}\n \treturn flow_hw_create_ctrl_flow(dev, proxy_dev,\n \t\t\t\t\tproxy_priv->hw_esw_zero_tbl,\n-\t\t\t\t\titems, 0, actions, 0, &flow_info);\n+\t\t\t\t\titems, 0, actions, 0, &flow_info, false);\n }\n \n int\n@@ -11876,11 +11895,11 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)\n \t\treturn 0;\n \treturn flow_hw_create_ctrl_flow(dev, dev,\n \t\t\t\t\tpriv->hw_tx_meta_cpy_tbl,\n-\t\t\t\t\teth_all, 0, copy_reg_action, 0, &flow_info);\n+\t\t\t\t\teth_all, 0, copy_reg_action, 0, &flow_info, false);\n }\n \n int\n-mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn)\n+mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_rte_flow_item_sq sq_spec = {\n@@ -11934,7 +11953,7 @@ mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn)\n \t\tactions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;\n \t}\n \treturn flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,\n-\t\t\t\t\titems, 0, actions, 0, &flow_info);\n+\t\t\t\t\titems, 0, actions, 0, &flow_info, external);\n }\n \n static uint32_t\n@@ -12065,7 +12084,7 @@ __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,\n \titems[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);\n \titems[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };\n \t/* Without VLAN filtering, only a single flow rule must be created. */\n-\treturn flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info);\n+\treturn flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);\n }\n \n static int\n@@ -12106,7 +12125,7 @@ __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,\n \t\t};\n \n \t\titems[1].spec = &vlan_spec;\n-\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info))\n+\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))\n \t\t\treturn -rte_errno;\n \t}\n \treturn 0;\n@@ -12150,7 +12169,7 @@ __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,\n \t\tif (!memcmp(mac, &cmp, sizeof(*mac)))\n \t\t\tcontinue;\n \t\tmemcpy(ð_spec.hdr.dst_addr.addr_bytes, mac->addr_bytes, RTE_ETHER_ADDR_LEN);\n-\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info))\n+\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))\n \t\t\treturn -rte_errno;\n \t}\n \treturn 0;\n@@ -12204,7 +12223,7 @@ __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,\n \n \t\t\titems[1].spec = &vlan_spec;\n \t\t\tif (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0,\n-\t\t\t\t\t\t &flow_info))\n+\t\t\t\t\t\t &flow_info, false))\n \t\t\t\treturn -rte_errno;\n \t\t}\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 7bdb897612..d7ecb149fa 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1494,13 +1494,13 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev)\n \t\t\tcontinue;\n \t\tqueue = mlx5_txq_get_sqn(txq);\n \t\tif ((priv->representor || priv->master) && config->dv_esw_en) {\n-\t\t\tif (mlx5_flow_hw_esw_create_sq_miss_flow(dev, queue)) {\n+\t\t\tif (mlx5_flow_hw_esw_create_sq_miss_flow(dev, queue, false)) {\n \t\t\t\tmlx5_txq_release(dev, i);\n \t\t\t\tgoto error;\n \t\t\t}\n \t\t}\n \t\tif (config->dv_esw_en && config->repr_matching) {\n-\t\t\tif (mlx5_flow_hw_tx_repr_matching_flow(dev, queue)) {\n+\t\t\tif (mlx5_flow_hw_tx_repr_matching_flow(dev, queue, false)) {\n \t\t\t\tmlx5_txq_release(dev, i);\n \t\t\t\tgoto error;\n \t\t\t}\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex ccdf2ffb14..1ac43548b2 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -1311,10 +1311,10 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num)\n \t}\n #ifdef HAVE_MLX5_HWS_SUPPORT\n \tif (priv->sh->config.dv_flow_en == 2) {\n-\t\tif (mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num))\n+\t\tif (mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num, true))\n \t\t\treturn -rte_errno;\n \t\tif (priv->sh->config.repr_matching &&\n-\t\t mlx5_flow_hw_tx_repr_matching_flow(dev, sq_num)) {\n+\t\t mlx5_flow_hw_tx_repr_matching_flow(dev, sq_num, true)) {\n \t\t\tmlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num);\n \t\t\treturn -rte_errno;\n \t\t}\n", "prefixes": [ "2/2" ] }