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GET /api/patches/133658/?format=api
{ "id": 133658, "url": "http://patches.dpdk.org/api/patches/133658/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231031122512.434686-9-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231031122512.434686-9-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231031122512.434686-9-getelson@nvidia.com", "date": "2023-10-31T12:25:10", "name": "[08/10] net/mlx5/hws: allow jump to TIR over FDB", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": true, "hash": "cf776d7087b434e50e85a128eb1e14eca7cf2960", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231031122512.434686-9-getelson@nvidia.com/mbox/", "series": [ { "id": 30072, "url": "http://patches.dpdk.org/api/series/30072/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30072", "date": "2023-10-31T12:25:02", "name": "net/mlx5/hws: IPSEC reparse submission", "version": 1, "mbox": "http://patches.dpdk.org/series/30072/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133658/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/133658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=iFzDyUXonLaX8TuZeWTEPqMhLp2qxz0lBsgdqhJP1RAAQ6xI1OHGxQYez5M3LMq65KvcvrnSegeow7m1jG7xeHcvc6k6J5g5ycYH83NsXXgswvnmg3XIWmTa4ohq4Tpw+OEDfeDwzfkDoIJwDAI1nhJhK1dBl71uYKMaJvf8IKzwQWnYcqbYjWeEJ6KxuL9i7iU8hOHiuPHabO7isQr5QaeHYqd2LJj6DlxSGnHOozHlVDlY9gQW6yqEj/DbEaY2dIeq2fSlPU7EGGwHFmAJLjC3f/LLCBuvI+z4FKwi3PX1ypeFzTNgZGCy5BM5anSl76c54Ae8MxYBzwxuFEZOdw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, \"Alex\n Vesker\" <valex@nvidia.com>, Erez Shitrit <erezsh@nvidia.com>, Matan Azrad\n <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 08/10] net/mlx5/hws: allow jump to TIR over FDB", "Date": "Tue, 31 Oct 2023 14:25:10 +0200", "Message-ID": "<20231031122512.434686-9-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231031122512.434686-1-getelson@nvidia.com>", "References": "<20231031122512.434686-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MN1PEPF0000ECDA:EE_|CH2PR12MB5019:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0ca42693-2351-4ebc-c303-08dbda0c9262", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", 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CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(396003)(136003)(376002)(346002)(230922051799003)(451199024)(64100799003)(82310400011)(186009)(1800799009)(40470700004)(46966006)(36840700001)(41300700001)(5660300002)(70586007)(70206006)(54906003)(316002)(6916009)(8676002)(4326008)(8936002)(55016003)(40480700001)(40460700003)(82740400003)(7636003)(356005)(47076005)(83380400001)(478600001)(2906002)(16526019)(6286002)(26005)(36756003)(426003)(7696005)(107886003)(1076003)(86362001)(2616005)(336012)(36860700001)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Oct 2023 12:26:13.1434 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0ca42693-2351-4ebc-c303-08dbda0c9262", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MN1PEPF0000ECDA.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB5019", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alex Vesker <valex@nvidia.com>\n\nCurrent TIR action is allowed to be used only for NIC RX,\nthis will allow TIR action over FDB for RX traffic in case\nof TX traffic packets will be dropped.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\nReviewed-by: Erez Shitrit <erezsh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 2 ++\n drivers/net/mlx5/hws/mlx5dr_action.c | 27 ++++++++++++++++++++++-----\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 4 ++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 +\n 4 files changed, 29 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 40e461cb82..bb2b990d5b 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -2418,6 +2418,8 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits {\n \tu8 reserved_at_180[0x10];\n \tu8 ste_format_gen_wqe[0x10];\n \tu8 linear_match_definer_reg_c3[0x20];\n+\tu8 fdb_jump_to_tir_stc[0x1];\n+\tu8 reserved_at_1c1[0x1f];\n };\n \n union mlx5_ifc_hca_cap_union_bits {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c\nindex 1a6296a728..05b6e97576 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.c\n@@ -445,6 +445,7 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,\n \t\tbreak;\n \n \tcase MLX5_IFC_STC_ACTION_TYPE_CRYPTO_IPSEC_ENCRYPTION:\n+\t\t/* Encrypt is allowed on RX side, requires mask in case of FDB */\n \t\tif (fw_tbl_type == FS_FT_FDB_RX) {\n \t\t\tfixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_NOP;\n \t\t\tfixup_stc_attr->action_offset = stc_attr->action_offset;\n@@ -454,6 +455,7 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,\n \t\tbreak;\n \n \tcase MLX5_IFC_STC_ACTION_TYPE_CRYPTO_IPSEC_DECRYPTION:\n+\t\t/* Decrypt is allowed on TX side, requires mask in case of FDB */\n \t\tif (fw_tbl_type == FS_FT_FDB_TX) {\n \t\t\tfixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_NOP;\n \t\t\tfixup_stc_attr->action_offset = stc_attr->action_offset;\n@@ -463,12 +465,10 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,\n \t\tbreak;\n \n \tcase MLX5_IFC_STC_ACTION_TYPE_TRAILER:\n-\t\tif (table_type != MLX5DR_TABLE_TYPE_FDB)\n-\t\t\tbreak;\n-\n+\t\t/* Trailer has FDB limitations on RX and TX based on operation */\n \t\tval = stc_attr->reformat_trailer.op;\n-\t\tif ((val == MLX5DR_ACTION_TRAILER_OP_INSERT && !is_mirror) ||\n-\t\t (val == MLX5DR_ACTION_TRAILER_OP_REMOVE && is_mirror)) {\n+\t\tif ((val == MLX5DR_ACTION_TRAILER_OP_INSERT && fw_tbl_type == FS_FT_FDB_RX) ||\n+\t\t (val == MLX5DR_ACTION_TRAILER_OP_REMOVE && fw_tbl_type == FS_FT_FDB_TX)) {\n \t\t\tfixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_NOP;\n \t\t\tfixup_stc_attr->action_offset = stc_attr->action_offset;\n \t\t\tfixup_stc_attr->stc_offset = stc_attr->stc_offset;\n@@ -476,6 +476,16 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,\n \t\t}\n \t\tbreak;\n \n+\tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR:\n+\t\t/* TIR is allowed on RX side, requires mask in case of FDB */\n+\t\tif (fw_tbl_type == FS_FT_FDB_TX) {\n+\t\t\tfixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_DROP;\n+\t\t\tfixup_stc_attr->action_offset = MLX5DR_ACTION_OFFSET_HIT;\n+\t\t\tfixup_stc_attr->stc_offset = stc_attr->stc_offset;\n+\t\t\tuse_fixup = true;\n+\t\t}\n+\t\tbreak;\n+\n \tdefault:\n \t\tbreak;\n \t}\n@@ -976,6 +986,13 @@ mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx,\n \t\treturn NULL;\n \t}\n \n+\tif ((flags & MLX5DR_ACTION_FLAG_ROOT_FDB) ||\n+\t (flags & MLX5DR_ACTION_FLAG_HWS_FDB && !ctx->caps->fdb_tir_stc)) {\n+\t\tDR_LOG(ERR, \"TIR action not support on FDB\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn NULL;\n+\t}\n+\n \tif (!is_local) {\n \t\tDR_LOG(ERR, \"TIR should be created on local ibv_device, flags: 0x%x\",\n \t\t flags);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex 0ba4774f08..135d31dca1 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -1275,6 +1275,10 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,\n \t\tcaps->supp_ste_format_gen_wqe = MLX5_GET(query_hca_cap_out, out,\n \t\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n \t\t\t\t\t\t\t ste_format_gen_wqe);\n+\n+\t\tcaps->fdb_tir_stc = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t fdb_jump_to_tir_stc);\n \t}\n \n \tif (caps->eswitch_manager) {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex c082157538..cb27212a5b 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -241,6 +241,7 @@ struct mlx5dr_cmd_query_caps {\n \tuint8_t log_header_modify_argument_granularity;\n \tuint8_t log_header_modify_argument_max_alloc;\n \tuint8_t sq_ts_format;\n+\tuint8_t fdb_tir_stc;\n \tuint64_t definer_format_sup;\n \tuint32_t trivial_match_definer;\n \tuint32_t vhca_id;\n", "prefixes": [ "08/10" ] }