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GET /api/patches/133274/?format=api
{ "id": 133274, "url": "http://patches.dpdk.org/api/patches/133274/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231024175132.1435553-5-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231024175132.1435553-5-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231024175132.1435553-5-akozyrev@nvidia.com", "date": "2023-10-24T17:51:29", "name": "[v3,4/7] doc: add PMD ptype item limitations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f7147dc567b93702683349c3d010da77efc93cbd", "submitter": { "id": 1873, "url": "http://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231024175132.1435553-5-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29969, "url": "http://patches.dpdk.org/api/series/29969/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29969", "date": "2023-10-24T17:51:25", "name": "ptype matching support in mlx5", "version": 3, "mbox": "http://patches.dpdk.org/series/29969/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133274/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133274/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4FF484316B;\n\tTue, 24 Oct 2023 19:53:04 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9AB8B427DF;\n\tTue, 24 Oct 2023 19:52:33 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2049.outbound.protection.outlook.com [40.107.95.49])\n by mails.dpdk.org (Postfix) with ESMTP id 2000C427DE\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH v3 4/7] doc: add PMD ptype item limitations", "Date": "Tue, 24 Oct 2023 20:51:29 +0300", "Message-ID": "<20231024175132.1435553-5-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231024175132.1435553-1-akozyrev@nvidia.com>", "References": "<20230828182251.3917624-1-akozyrev@nvidia.com>\n <20231024175132.1435553-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS3PEPF000099DA:EE_|DS0PR12MB8246:EE_", "X-MS-Office365-Filtering-Correlation-Id": "44b19673-3219-4bf3-eab9-08dbd4b9fe0a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n XuzyATz0X7lWJtYU3xYHKkIlpT8G93JzkGVlhGPjGEK62CvIyuETdjVswaFFFLX+6t5aKuKu4L46X8lAFIZ7f+R/YX49QNVkdG15d7y1dbcier11wG2msywYnqNiAz3YmGN9kELQwZUKEDGqkLvTpWTAMb/moPNwBvWoWXdHdzFO6sABrpHyKLKZ+FR3ICylWHATyMHyUQpR/IdctaFCvVXUqry9aVpE271FlC6X2tbil4aMx9TomtC6XyLIezYWXLVkZxW1wDS4bxBO89C+ECnnD6W8bVuzT0Gsz4k/CidV8VzbXajDBsI1e2ZkBJDzhDU9Cbv/PV7LMWgsqVW1LsX7qxJbkMnOMlud0n6KAQJxKF99XEArz0+qt7+WYoPd5WiGRuVwjWbvc1Rkkye/GI2rv+ayi9TM6bGel8sktCs/R64Gg+9a13SEVvxJ7NeUa6qbKxj619egnYTTT18DKIFu5TcelVOCwp9RSatPXe8uV35uC7pv9zJ29fJ+gTIdCs88aLCxYQ6AQ/yGsRCqxZOukStVkdVqtk6wXI+mNYizfvTyFLCJGSgDLa5404MYGCA4BYA2tXpNOX5lsPazN2/Vy5NX5HymUBaeka2pDQuOcbN0GS2HgzNfwezJ0SCW7+DMZHF82N1X/DDJo/Y5vuOnuHBxm5qXZMBDY/iK5rn1n8q7buHzBO2W7pJRbR2Qwz42IXFAAcDrpoxlvi48fATbk+f7btXN8KPh5YJUpIHnmCyAZJGmfgXmfwOICuGL", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(396003)(376002)(39860400002)(136003)(230922051799003)(451199024)(186009)(82310400011)(1800799009)(64100799003)(40470700004)(46966006)(36840700001)(26005)(40480700001)(36756003)(40460700003)(7636003)(6916009)(54906003)(70586007)(86362001)(316002)(356005)(82740400003)(36860700001)(83380400001)(2616005)(426003)(16526019)(1076003)(107886003)(336012)(6666004)(478600001)(70206006)(47076005)(41300700001)(5660300002)(4326008)(8676002)(8936002)(2906002)(21314003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Oct 2023 17:52:28.9380 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 44b19673-3219-4bf3-eab9-08dbd4b9fe0a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS3PEPF000099DA.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB8246", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nAdd limitations for ptype item support in \"mlx5.rst\" file.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 15 +++++++++++++++\n 2 files changed, 16 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex fc67415c6c..e3927ab4df 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -86,6 +86,7 @@ nsh = Y\n nvgre = Y\n port_id = Y\n port_representor = Y\n+ptype = Y\n quota = Y\n tag = Y\n tcp = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 7086f3d1d4..c9e74948cc 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -646,6 +646,21 @@ Limitations\n - When using HWS flow engine (``dv_flow_en`` = 2),\n only meter mark action is supported.\n \n+- Ptype:\n+\n+ - Only supports HW steering (``dv_flow_en=2``).\n+ - The supported values are:\n+ L2: ``RTE_PTYPE_L2_ETHER``, ``RTE_PTYPE_L2_ETHER_VLAN``, ``RTE_PTYPE_L2_ETHER_QINQ``\n+ L3: ``RTE_PTYPE_L3_IPV4``, ``RTE_PTYPE_L3_IPV6``\n+ L4: ``RTE_PTYPE_L4_TCP``, ``RTE_PTYPE_L4_UDP``, ``RTE_PTYPE_L4_ICMP``\n+ and their ``RTE_PTYPE_INNER_XXX`` counterparts as well as ``RTE_PTYPE_TUNNEL_ESP``.\n+ Any other values are not supported. Using them as a value will cause unexpected behavior.\n+ - Matching on both outer and inner IP fragmented is supported using ``RTE_PTYPE_L4_FRAG`` and\n+ ``RTE_PTYPE_INNER_L4_FRAG`` values. They are not part of L4 types, so they should be provided\n+ explicitly as a mask value during pattern template creation. Providing ``RTE_PTYPE_L4_MASK``\n+ during pattern template creation and ``RTE_PTYPE_L4_FRAG`` during flow rule creation\n+ will cause unexpected behavior.\n+\n - Integrity:\n \n - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n", "prefixes": [ "v3", "4/7" ] }