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GET /api/patches/133273/?format=api
{ "id": 133273, "url": "http://patches.dpdk.org/api/patches/133273/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231024175132.1435553-7-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231024175132.1435553-7-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231024175132.1435553-7-akozyrev@nvidia.com", "date": "2023-10-24T17:51:31", "name": "[v3,6/7] net/mlx5/hws: remove csum check from L3 ok check", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "003f82a45ca09281a012dfaf097f8b15319c0092", "submitter": { "id": 1873, "url": "http://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231024175132.1435553-7-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29969, "url": "http://patches.dpdk.org/api/series/29969/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29969", "date": "2023-10-24T17:51:25", "name": "ptype matching support in mlx5", "version": 3, "mbox": "http://patches.dpdk.org/series/29969/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133273/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133273/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 376F74316B;\n\tTue, 24 Oct 2023 19:52:57 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6659B41611;\n\tTue, 24 Oct 2023 19:52:32 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2066.outbound.protection.outlook.com [40.107.93.66])\n by mails.dpdk.org (Postfix) with ESMTP id 0695041149\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH v3 6/7] net/mlx5/hws: remove csum check from L3 ok check", "Date": "Tue, 24 Oct 2023 20:51:31 +0300", "Message-ID": "<20231024175132.1435553-7-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231024175132.1435553-1-akozyrev@nvidia.com>", "References": "<20230828182251.3917624-1-akozyrev@nvidia.com>\n <20231024175132.1435553-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF0001709B:EE_|DM6PR12MB4122:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1a678d53-7eeb-4ffd-de80-08dbd4b9fd24", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n aLY+rEqKx/PEtwBloEX/iLbFUUDA+ZtfqWatq9fYz7nTI+TFs4ApG97YyZhvFqamIcCk4zXpiDktfHg2Le6hMil/52pkRvx1LYQBSPjzLT0oUh9wztdlmhlHSKhIUdafDAMSK9yauHX8K2hueLIlWNs/zulMqgrfXopQY0dAJAAgeCMu7pbuFsjt5Gt5hobiRpaAhJ5mTYGJQQiwHfbpeMEbPBAd+At81DMV6enTwS4x144BUggl80Afb6NWm2So1dNVX/6d7AxSnsodCdXhAQFIUrBVHNGtivqSj2EYUZZShmTm8njwRsoNt6GV5AwVA6VYUtVzuD8FOJv1iyHaiG3mJoB1AXCLWNlHb7SP0JLdmD23apIjNMs6/xscixTrA61dYDvGv6L6BG5FcH4ext18Of1CJgC3IZYKt8nSrAuhJpHlw8q9rHp+K8OAdCPb6nU2iiTB1fANxH6wlbQmcJGefpvBg+aB6WMwnWKE4GendR+ba9NM/daJD0XCx51AqPIfSPEBKsEjVfpzSOziR14b24NQkKLLrCxK7OqieYXVTRJb2W6QIS1MTEVfg9vmn8Opa/2aJ4+J3DOM5DLf5ZdIMAoaSGzxco0V8hQstMsuI7Gc7hD9GnlHpJPIET6rABubu72ELn/9CCM3xCO6qtbdARUbflj8fDO5XgpjbfP3PgI2CSxaWz4jLbISV2KdODxZUaNlYL70KqUx5DPrMxpS0mcdbkSLghkbbImN2Sf+bRWjeJs8ClZecXfTLiyK", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(39860400002)(376002)(346002)(396003)(230922051799003)(82310400011)(451199024)(1800799009)(186009)(64100799003)(46966006)(40470700004)(36840700001)(36860700001)(2906002)(47076005)(5660300002)(83380400001)(41300700001)(82740400003)(7636003)(356005)(426003)(336012)(16526019)(1076003)(107886003)(26005)(40480700001)(40460700003)(6666004)(4326008)(2616005)(8676002)(8936002)(70206006)(316002)(54906003)(6916009)(86362001)(36756003)(478600001)(70586007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Oct 2023 17:52:28.2584 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1a678d53-7eeb-4ffd-de80-08dbd4b9fd24", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF0001709B.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4122", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nThis patch changes the integrity item behavior for HW steering.\n\nOld behavior: the \"ipv4_csum_ok\" checks only IPv4 checksum and \"l3_ok\"\nchecks everything is ok including IPv4 checksum.\n\nNew behavior: the \"l3_ok\" checks everything is ok excluding IPv4\nchecksum.\n\nThis change enables matching \"l3_ok\" in IPv6 packets since for IPv6\npackets \"ipv4_csum_ok\" is always miss.\nFor SW steering the old behavior is kept as same as for L4 ok.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 11 ++++++++---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++----\n 2 files changed, 10 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex c9e74948cc..8d7e0aad7e 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -663,12 +663,13 @@ Limitations\n \n - Integrity:\n \n- - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.\n - ``level`` value 0 references outer headers.\n - Negative integrity item verification is not supported.\n- - Multiple integrity items not supported in a single flow rule.\n- - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.\n+ - With SW steering (``dv_flow_en=1``)\n+ - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n+ - Multiple integrity items not supported in a single flow rule.\n+ - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.\n For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,\n TCP or UDP, must be in the rule pattern as well::\n \n@@ -676,6 +677,10 @@ Limitations\n \n flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end …\n \n+ - With HW steering (``dv_flow_en=2``)\n+ - The ``l3_ok`` field represents all L3 checks, but nothing about whether IPv4 checksum ok.\n+ - The ``l4_ok`` field represents all L4 checks including L4 checksum ok.\n+\n - Connection tracking:\n \n - Cannot co-exist with ASO meter, ASO age action in a single flow rule.\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 0e1035c6bd..c752896ca7 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -380,10 +380,8 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,\n \tuint32_t ok1_bits = 0;\n \n \tif (v->l3_ok)\n-\t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) |\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK);\n+\t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :\n+\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK);\n \n \tif (v->ipv4_csum_ok)\n \t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :\n", "prefixes": [ "v3", "6/7" ] }