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GET /api/patches/133271/?format=api
{ "id": 133271, "url": "http://patches.dpdk.org/api/patches/133271/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231024175132.1435553-3-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231024175132.1435553-3-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231024175132.1435553-3-akozyrev@nvidia.com", "date": "2023-10-24T17:51:27", "name": "[v3,2/7] net/mlx5: add support for ptype match in hardware steering", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3adf53cbb2bbffc50e44480165807f28a0ce6233", "submitter": { "id": 1873, "url": "http://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231024175132.1435553-3-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29969, "url": "http://patches.dpdk.org/api/series/29969/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29969", "date": "2023-10-24T17:51:25", "name": "ptype matching support in mlx5", "version": 3, "mbox": "http://patches.dpdk.org/series/29969/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133271/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133271/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D15074316B;\n\tTue, 24 Oct 2023 19:52:40 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D639440EE4;\n\tTue, 24 Oct 2023 19:52:26 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2043.outbound.protection.outlook.com [40.107.95.43])\n by mails.dpdk.org (Postfix) with ESMTP id 4BC0640EE2\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH v3 2/7] net/mlx5: add support for ptype match in hardware\n steering", "Date": "Tue, 24 Oct 2023 20:51:27 +0300", "Message-ID": "<20231024175132.1435553-3-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231024175132.1435553-1-akozyrev@nvidia.com>", "References": "<20230828182251.3917624-1-akozyrev@nvidia.com>\n <20231024175132.1435553-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS3PEPF000099DA:EE_|PH0PR12MB7959:EE_", "X-MS-Office365-Filtering-Correlation-Id": "28601704-9696-497f-3b40-08dbd4b9f8ca", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n WQflzg6cMYqgH2MMLaziL0MG9OFoNWclz8bGW7qEjtujN+s+brO5qJ2zjCqYwGwvClgyPoZRJ5qBp0szZ8jfmmzDpqE9oWWpVFqf1Cjdugnll8M2CAKeIf10N7xgvks7YoHi82vfC6HFIKd31iktrpQG8hkDtximdWLumVLOCpobHq6wzGML1NkIwhc14mlzfVz1he01WKRZkOkMTrQ2hivvJ4tnhObh8VBYl3gxhp/b8W6YdrxqLsoFcsbOx7TrEvwrYBdxRbl9ZzulsG7Tp1Xr/kBp3W5+uRWuG8ObR8xQQ8CDN1OLZ6MqWQJUTUynNUPcP1V+wZyF+0DrXr8WuHdk1fOy80oSy8hCkgjOZalVLvtJyh9tch7g5mnkDE7byCV2kRC1SH6EgFpk9ygu4EkQqyo4OKfEcWnYJ1NRn5TqxSYn/qqqChM44pvmHSLYWgeX5DQfevpRUb4deGXuF2FV5lTzOiZ6lKCKb7drwW6lZTPPWvI8EGQlNCkqY+OgbVyg/zq+B8ZUue2Ti8Cd+MHTRB+QGyfajDhYnGhF9zxlsUxAl33yCz/3FHkg4W3U5x5whOmaopyUh060Dl4UOBEC9oajm/1+gBZWM6pWPrC6cq9OTE4VRut/Rf6mY28w3JJmykEra6ntepuAvgsXHxlG0IXb3B5YX7CgMieqg8hLY/Ay22s0BTYxPtX/9PmZckclKRgoGriotn5jBip+LrTuJg90sFSKYNKTLnYeK3zDE8niTZYJf8hskItx2dI9", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(39860400002)(376002)(346002)(136003)(230922051799003)(64100799003)(1800799009)(186009)(451199024)(82310400011)(36840700001)(40470700004)(46966006)(40460700003)(41300700001)(2906002)(54906003)(6666004)(70206006)(82740400003)(316002)(70586007)(107886003)(6916009)(1076003)(7636003)(16526019)(40480700001)(336012)(47076005)(426003)(83380400001)(36860700001)(86362001)(5660300002)(4326008)(2616005)(478600001)(36756003)(8936002)(8676002)(356005)(26005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Oct 2023 17:52:20.9535 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 28601704-9696-497f-3b40-08dbd4b9f8ca", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS3PEPF000099DA.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7959", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The packet type matching provides quick way of finding out\nL2/L3/L4 protocols in a given packet. That helps with\noptimized flow rules matching, eliminating the need of\nstacking all the packet headers in the matching criteria.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 161 ++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 7 ++\n drivers/net/mlx5/mlx5_flow.h | 3 +\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 4 files changed, 172 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 95b5d4b70e..8d846984e7 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -16,11 +16,15 @@\n #define STE_NO_VLAN\t0x0\n #define STE_SVLAN\t0x1\n #define STE_CVLAN\t0x2\n+#define STE_NO_L3\t0x0\n #define STE_IPV4\t0x1\n #define STE_IPV6\t0x2\n+#define STE_NO_L4\t0x0\n #define STE_TCP\t\t0x1\n #define STE_UDP\t\t0x2\n #define STE_ICMP\t0x3\n+#define STE_NO_TUN\t0x0\n+#define STE_ESP\t\t0x3\n \n #define MLX5DR_DEFINER_QUOTA_BLOCK 0\n #define MLX5DR_DEFINER_QUOTA_PASS 2\n@@ -277,6 +281,82 @@ mlx5dr_definer_conntrack_tag(struct mlx5dr_definer_fc *fc,\n \tDR_SET(tag, reg_value, fc->byte_off, fc->bit_off, fc->bit_mask);\n }\n \n+static void\n+mlx5dr_definer_ptype_l2_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tbool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L2_I);\n+\tconst struct rte_flow_item_ptype *v = item_spec;\n+\tuint32_t packet_type = v->packet_type &\n+\t\t(inner ? RTE_PTYPE_INNER_L2_MASK : RTE_PTYPE_L2_MASK);\n+\tuint8_t l2_type = STE_NO_VLAN;\n+\n+\tif (packet_type == (inner ? RTE_PTYPE_INNER_L2_ETHER : RTE_PTYPE_L2_ETHER))\n+\t\tl2_type = STE_NO_VLAN;\n+\telse if (packet_type == (inner ? RTE_PTYPE_INNER_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER_VLAN))\n+\t\tl2_type = STE_CVLAN;\n+\telse if (packet_type == (inner ? RTE_PTYPE_INNER_L2_ETHER_QINQ : RTE_PTYPE_L2_ETHER_QINQ))\n+\t\tl2_type = STE_SVLAN;\n+\n+\tDR_SET(tag, l2_type, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n+static void\n+mlx5dr_definer_ptype_l3_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tbool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L3_I);\n+\tconst struct rte_flow_item_ptype *v = item_spec;\n+\tuint32_t packet_type = v->packet_type &\n+\t\t(inner ? RTE_PTYPE_INNER_L3_MASK : RTE_PTYPE_L3_MASK);\n+\tuint8_t l3_type = STE_NO_L3;\n+\n+\tif (packet_type == (inner ? RTE_PTYPE_INNER_L3_IPV4 : RTE_PTYPE_L3_IPV4))\n+\t\tl3_type = STE_IPV4;\n+\telse if (packet_type == (inner ? RTE_PTYPE_INNER_L3_IPV6 : RTE_PTYPE_L3_IPV6))\n+\t\tl3_type = STE_IPV6;\n+\n+\tDR_SET(tag, l3_type, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n+static void\n+mlx5dr_definer_ptype_l4_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tbool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_L4_I);\n+\tconst struct rte_flow_item_ptype *v = item_spec;\n+\tuint32_t packet_type = v->packet_type &\n+\t\t(inner ? RTE_PTYPE_INNER_L4_MASK : RTE_PTYPE_L4_MASK);\n+\tuint8_t l4_type = STE_NO_L4;\n+\n+\tif (packet_type == (inner ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP))\n+\t\tl4_type = STE_TCP;\n+\telse if (packet_type == (inner ? RTE_PTYPE_INNER_L4_UDP : RTE_PTYPE_L4_UDP))\n+\t\tl4_type = STE_UDP;\n+\telse if (packet_type == (inner ? RTE_PTYPE_INNER_L4_ICMP : RTE_PTYPE_L4_ICMP))\n+\t\tl4_type = STE_ICMP;\n+\n+\tDR_SET(tag, l4_type, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n+static void\n+mlx5dr_definer_ptype_tunnel_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\tconst void *item_spec,\n+\t\t\t\tuint8_t *tag)\n+{\n+\tconst struct rte_flow_item_ptype *v = item_spec;\n+\tuint32_t packet_type = v->packet_type & RTE_PTYPE_TUNNEL_MASK;\n+\tuint8_t tun_type = STE_NO_TUN;\n+\n+\tif (packet_type == RTE_PTYPE_TUNNEL_ESP)\n+\t\ttun_type = STE_ESP;\n+\n+\tDR_SET(tag, tun_type, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n static void\n mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,\n \t\t\t const void *item_spec,\n@@ -1709,6 +1789,83 @@ mlx5dr_definer_conv_item_gre_key(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t struct rte_flow_item *item,\n+\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_ptype *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (!(m->packet_type &\n+\t (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK | RTE_PTYPE_TUNNEL_MASK |\n+\t RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK | RTE_PTYPE_INNER_L4_MASK))) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_L2_MASK) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L2, false)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_l2_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, first_vlan_qualifier, false);\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_INNER_L2_MASK) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L2, true)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_l2_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, first_vlan_qualifier, true);\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_L3_MASK) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L3, false)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_l3_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, l3_type, false);\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_INNER_L3_MASK) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L3, true)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_l3_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, l3_type, true);\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_L4_MASK) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_l4_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, l4_type, false);\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_INNER_L4_MASK) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_l4_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, l4_type, true);\n+\t}\n+\n+\tif (m->packet_type & RTE_PTYPE_TUNNEL_MASK) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ptype_tunnel_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, false);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd,\n \t\t\t\t struct rte_flow_item *item,\n@@ -2332,6 +2489,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_IB_BTH;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_PTYPE:\n+\t\t\tret = mlx5dr_definer_conv_item_ptype(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_PTYPE;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex f5a541bc17..ea07f55d52 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -141,6 +141,13 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_IB_L4_OPCODE,\n \tMLX5DR_DEFINER_FNAME_IB_L4_QPN,\n \tMLX5DR_DEFINER_FNAME_IB_L4_A,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_L2_O,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_L2_I,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_L3_O,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_L3_I,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_L4_O,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_L4_I,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,\n \tMLX5DR_DEFINER_FNAME_MAX,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 903ff66d72..98b267245c 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -233,6 +233,9 @@ enum mlx5_feature_name {\n /* IB BTH ITEM. */\n #define MLX5_FLOW_ITEM_IB_BTH (1ull << 51)\n \n+/* PTYPE ITEM */\n+#define MLX5_FLOW_ITEM_PTYPE (1ull << 52)\n+\n /* NSH ITEM */\n #define MLX5_FLOW_ITEM_NSH (1ull << 53)\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 6fcf654e4a..34b3c9e6ad 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5382,6 +5382,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_ESP:\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n \t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\tcase RTE_FLOW_ITEM_TYPE_PTYPE:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "v3", "2/7" ] }