Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132300/?format=api
{ "id": 132300, "url": "http://patches.dpdk.org/api/patches/132300/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231004122432.3255418-1-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231004122432.3255418-1-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231004122432.3255418-1-jerinj@marvell.com", "date": "2023-10-04T12:24:31", "name": "[v2,1/2] common/cnxk: fix direct rte symbol usage", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6dcc182d67dbb3954059f5cc083a95d050e54225", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231004122432.3255418-1-jerinj@marvell.com/mbox/", "series": [ { "id": 29733, "url": "http://patches.dpdk.org/api/series/29733/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29733", "date": "2023-10-04T12:24:31", "name": "[v2,1/2] common/cnxk: fix direct rte symbol usage", "version": 2, "mbox": "http://patches.dpdk.org/series/29733/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/132300/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/132300/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AA11C426B6;\n\tWed, 4 Oct 2023 14:24:52 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7ADDE402CF;\n\tWed, 4 Oct 2023 14:24:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id F1FB5402DB\n for <dev@dpdk.org>; Wed, 4 Oct 2023 14:24:49 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3945tsqQ016836; Wed, 4 Oct 2023 05:24:49 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3th2b6h3mm-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 04 Oct 2023 05:24:48 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Wed, 4 Oct 2023 05:24:46 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Wed, 4 Oct 2023 05:24:46 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n by maili.marvell.com (Postfix) with ESMTP id 0F7523F7050;\n Wed, 4 Oct 2023 05:24:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=xgMhj1y62kOC1d77HRFZAyKzkVRYWzS/8lXvbhKQAfY=;\n b=bZmiz+fDcCell0Nfq4ubi/35OaI0h0ktGx8bbvcdP4K38XCtTfRXoZt+C2OPMvffUu44\n d1d8uiYgE3G60weZ6GeJcKvTi8XazUhfnEsIu1UL0E3V0EdPjmmCE9n8mmhs2c5cYHeA\n RCT5sJox2j4/7XP+Diq7HmY7Q+mljtVlKeQpzgndy3AWuo1DE+3HSwrxxk5bG6VQ4vCG\n LS6R27TYfAs1FQgyXP8fdE/wF5kpi96ZPORgx+t2BbqQoZeRT1rFywWd9kK9rqm5KkE7\n YeEZC227oX6b7RYwSIvneqXF9fKSZKGAxkN/rxbDJPtKVjZF5PFdj2HZ/D/5eai9o8dd jA==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>,\n Long Li <longli@microsoft.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>,\n David Marchand <david.marchand@redhat.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Thomas Monjalon <thomas@monjalon.net>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>", "CC": "Jerin Jacob <jerinj@marvell.com>", "Subject": "[dpdk-dev] [PATCH v2 1/2] common/cnxk: fix direct rte symbol usage", "Date": "Wed, 4 Oct 2023 17:54:31 +0530", "Message-ID": "<20231004122432.3255418-1-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20231003183956.1270510-1-jerinj@marvell.com>", "References": "<20231003183956.1270510-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "Gs2u1Q06ZosmDneX-vUb051qHOZzzObo", "X-Proofpoint-GUID": "Gs2u1Q06ZosmDneX-vUb051qHOZzzObo", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-04_04,2023-10-02_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe common code is shared between different driver environments,\nintroduce missing plt_ abstractions of missing rte_ symbols and\nuse plt symbols to avoid changing roc_* files.\n\nFixes: 3d4e27fd7ff0 (\"use abstracted bit count functions\")\nFixes: a7ba40b2b1bf (\"drivers: convert to internal control threads\")\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\nv2:\n- Remove thread name change (David)\n- Split REE changes as seperate patch to enable backporting (David)\n\n drivers/common/cnxk/roc_dev.c | 2 +-\n drivers/common/cnxk/roc_dev_priv.h | 2 +-\n drivers/common/cnxk/roc_nix_inl_dev.c | 2 +-\n drivers/common/cnxk/roc_nix_inl_priv.h | 2 +-\n drivers/common/cnxk/roc_nix_tm.c | 2 +-\n drivers/common/cnxk/roc_nix_tm_utils.c | 2 +-\n drivers/common/cnxk/roc_npa.c | 2 +-\n drivers/common/cnxk/roc_npc.c | 2 +-\n drivers/common/cnxk/roc_npc.h | 2 +-\n drivers/common/cnxk/roc_npc_mcam.c | 8 ++++----\n drivers/common/cnxk/roc_platform.h | 8 +++++++-\n 11 files changed, 20 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex e41235ea8a..865e2f97c7 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -1166,7 +1166,7 @@ dev_active_vfs(struct dev *dev)\n \tint i, count = 0;\n \n \tfor (i = 0; i < MAX_VFPF_DWORD_BITS; i++)\n-\t\tcount += rte_popcount32(dev->active_vfs[i]);\n+\t\tcount += plt_popcount32(dev->active_vfs[i]);\n \n \treturn count;\n }\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex c1a37aa4f0..5b2c5096f8 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -73,7 +73,7 @@ dev_is_afvf(uint16_t pf_func)\n struct mbox_sync {\n \tbool start_thread;\n \tuint8_t msg_avail;\n-\trte_thread_t pfvf_msg_thread;\n+\tplt_thread_t pfvf_msg_thread;\n \tpthread_cond_t pfvf_msg_cond;\n \tpthread_mutex_t mutex;\n };\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex 6aa191410b..bde436662b 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -1028,7 +1028,7 @@ roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev)\n \n \tif (inl_dev->set_soft_exp_poll) {\n \t\tsoft_exp_poll_thread_exit = true;\n-\t\trte_thread_join(inl_dev->soft_exp_poll_thread, NULL);\n+\t\tplt_thread_join(inl_dev->soft_exp_poll_thread, NULL);\n \t\tplt_bitmap_free(inl_dev->soft_exp_ring_bmap);\n \t\tplt_free(inl_dev->soft_exp_ring_bmap_mem);\n \t\tplt_free(inl_dev->sa_soft_exp_ring);\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex b2b89227b1..3217f4ebc1 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -67,7 +67,7 @@ struct nix_inl_dev {\n \tstruct roc_cpt_lf cpt_lf;\n \n \t/* OUTB soft expiry poll thread */\n-\trte_thread_t soft_exp_poll_thread;\n+\tplt_thread_t soft_exp_poll_thread;\n \tuint32_t soft_exp_poll_freq;\n \tuint64_t *sa_soft_exp_ring;\n \tbool set_soft_exp_poll;\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex a24bce9e70..ece88b5e99 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -11,7 +11,7 @@ bitmap_ctzll(uint64_t slab)\n \tif (slab == 0)\n \t\treturn 0;\n \n-\treturn rte_ctz64(slab);\n+\treturn plt_ctz64(slab);\n }\n \n void\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex c14517c9ea..8e3da95a45 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -927,7 +927,7 @@ nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig)\n \t/* Count bit set */\n \tstart_pos = pos;\n \tdo {\n-\t\tcount += rte_popcount64(slab);\n+\t\tcount += plt_popcount64(slab);\n \t\tif (!plt_bitmap_scan(bmp, &pos, &slab))\n \t\t\tbreak;\n \t} while (pos != start_pos);\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 1943bc5420..b76b8e2342 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -400,7 +400,7 @@ bitmap_ctzll(uint64_t slab)\n \tif (slab == 0)\n \t\treturn 0;\n \n-\treturn rte_ctz64(slab);\n+\treturn plt_ctz64(slab);\n }\n \n static int\ndiff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c\nindex 94c8e94400..f36f5e42c8 100644\n--- a/drivers/common/cnxk/roc_npc.c\n+++ b/drivers/common/cnxk/roc_npc.c\n@@ -1435,7 +1435,7 @@ roc_npc_sdp_channel_get(struct roc_npc *roc_npc, uint16_t *chan_base, uint16_t *\n \tnum_chan = nix->rx_chan_cnt - 1;\n \tif (num_chan) {\n \t\trange = *chan_base ^ (*chan_base + num_chan);\n-\t\tnum_bits = (sizeof(uint32_t) * 8) - rte_clz32(range) - 1;\n+\t\tnum_bits = (sizeof(uint32_t) * 8) - plt_clz32(range) - 1;\n \t\t/* Set mask for (15 - numbits) MSB bits */\n \t\t*chan_mask = (uint16_t)~GENMASK(num_bits, 0);\n \t} else {\ndiff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h\nindex 5a7117eae4..cf7e6c9548 100644\n--- a/drivers/common/cnxk/roc_npc.h\n+++ b/drivers/common/cnxk/roc_npc.h\n@@ -359,7 +359,7 @@ struct roc_npc_flow_age {\n \tuint32_t aged_flows_cnt;\n \tuint32_t start_id;\n \tuint32_t end_id;\n-\trte_thread_t aged_flows_poll_thread;\n+\tplt_thread_t aged_flows_poll_thread;\n \tstruct plt_bitmap *aged_flows;\n \tvoid *age_mem;\n \tbool aged_flows_get_thread_exit;\ndiff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c\nindex 8ec4bef472..41edec7d8d 100644\n--- a/drivers/common/cnxk/roc_npc_mcam.c\n+++ b/drivers/common/cnxk/roc_npc_mcam.c\n@@ -745,7 +745,7 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, struct npc_\n \t\t * For all other rules, set LA LTYPE to match both 1st pass and 2nd pass ltypes.\n \t\t */\n \t\tif (pst->is_second_pass_rule || (!pst->is_second_pass_rule && pst->has_eth_type)) {\n-\t\t\tla_offset = rte_popcount32(npc->keyx_supp_nmask[flow->nix_intf] &\n+\t\t\tla_offset = plt_popcount32(npc->keyx_supp_nmask[flow->nix_intf] &\n \t\t\t\t\t\t ((1ULL << 9 /* LA offset */) - 1));\n \t\t\tla_offset *= 4;\n \n@@ -790,7 +790,7 @@ npc_set_vlan_ltype(struct npc_parse_state *pst)\n \tuint8_t lb_offset;\n \n \tlb_offset =\n-\t\trte_popcount32(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n+\t\tplt_popcount32(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n \t\t\t\t ((1ULL << NPC_LTYPE_LB_OFFSET) - 1));\n \tlb_offset *= 4;\n \n@@ -812,7 +812,7 @@ npc_set_ipv6ext_ltype_mask(struct npc_parse_state *pst)\n \tuint64_t val, mask;\n \n \tlc_offset =\n-\t\trte_popcount32(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n+\t\tplt_popcount32(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n \t\t\t\t ((1ULL << NPC_LTYPE_LC_OFFSET) - 1));\n \tlc_offset *= 4;\n \n@@ -835,7 +835,7 @@ npc_set_ipv6ext_ltype_mask(struct npc_parse_state *pst)\n \t * zero in LFLAG.\n \t */\n \tif (pst->npc->keyx_supp_nmask[pst->nix_intf] & (1ULL << NPC_LFLAG_LC_OFFSET)) {\n-\t\tlcflag_offset = rte_popcount32(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n+\t\tlcflag_offset = plt_popcount32(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n \t\t\t\t\t\t ((1ULL << NPC_LFLAG_LC_OFFSET) - 1));\n \t\tlcflag_offset *= 4;\n \ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 1e535a527d..ba23b2e0d7 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -137,6 +137,7 @@\n #define plt_seqcount_write_begin\trte_seqcount_write_begin\n #define plt_seqcount_write_end\t\trte_seqcount_write_end\n \n+#define plt_thread_t\t\t rte_thread_t\n #define plt_intr_callback_register rte_intr_callback_register\n #define plt_intr_callback_unregister rte_intr_callback_unregister\n #define plt_intr_disable\t rte_intr_disable\n@@ -146,7 +147,7 @@\n #define plt_thread_join\t rte_thread_join\n \n static inline bool\n-plt_thread_is_valid(rte_thread_t thr)\n+plt_thread_is_valid(plt_thread_t thr)\n {\n \treturn thr.opaque_id ? true : false;\n }\n@@ -209,6 +210,11 @@ plt_thread_is_valid(rte_thread_t thr)\n #define plt_bit_relaxed_set64 rte_bit_relaxed_set64\n #define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64\n \n+#define plt_popcount32\t\trte_popcount32\n+#define plt_popcount64\t\trte_popcount64\n+#define plt_clz32\t\trte_clz32\n+#define plt_ctz64\t\trte_ctz64\n+\n #define plt_mmap mmap\n #define PLT_PROT_READ PROT_READ\n #define PLT_PROT_WRITE PROT_WRITE\n", "prefixes": [ "v2", "1/2" ] }