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GET /api/patches/131520/?format=api
http://patches.dpdk.org/api/patches/131520/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230918021130.192982-5-simei.su@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230918021130.192982-5-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230918021130.192982-5-simei.su@intel.com", "date": "2023-09-18T02:11:16", "name": "[v4,04/18] common/idpf/base: initial PTP support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4dea5498e0c854375cc4f63a9afa77f3a31ec8cc", "submitter": { "id": 1298, "url": "http://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230918021130.192982-5-simei.su@intel.com/mbox/", "series": [ { "id": 29530, "url": "http://patches.dpdk.org/api/series/29530/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29530", "date": "2023-09-18T02:11:12", "name": "update idpf base code", "version": 4, "mbox": "http://patches.dpdk.org/series/29530/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131520/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/131520/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E1785425C9;\n\tMon, 18 Sep 2023 04:12:16 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2FB3D40691;\n\tMon, 18 Sep 2023 04:12:14 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id E93F54068A\n for <dev@dpdk.org>; Mon, 18 Sep 2023 04:12:11 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Sep 2023 19:11:15 -0700", "from dpdk-simei-icelake.sh.intel.com ([10.67.110.167])\n by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2023 19:11:13 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695003132; x=1726539132;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=0LPcb6RJlQ60xj8TEigwiUZ0qxJb7fQ3aWCgKi2HFgU=;\n b=dx/aOx8FfNrZA6wGYMi0xP2mbiW/ZgvTzhKnRI9NIqiGYiiuAm+BBAbd\n 6uwuTM0NAWXAPkCDAb9ZuGgdu2/lZDFhJB3ruc7kVPBxyU8yeO7eeTEez\n 1pKObnb32L/+chMj0rP/f9b98LXG6InvVxZ9A+xOg3hgiYF1SNJK+yxIJ\n ktgrBhdB7X6QLzqBp3JcSgm31Yq15ZbUHweyjCMrkV1khu8sU6W/eMI+a\n tQtz3MnIA5Tkox80DaGOCskk1ju+d9lBs5meBjj6zhokC/MfKFNqMULR7\n jGokIVEW7F8hVpAozO9dhFxycr34bvZAkkS5N9ha+aoQyA1D5qPN7ZG/d g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10836\"; a=\"359801591\"", "E=Sophos;i=\"6.02,155,1688454000\"; d=\"scan'208\";a=\"359801591\"", "E=McAfee;i=\"6600,9927,10836\"; a=\"815846811\"", "E=Sophos;i=\"6.02,155,1688454000\"; d=\"scan'208\";a=\"815846811\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com,\n wenjing.qiao@intel.com, Simei Su <simei.su@intel.com>,\n Milena Olech <milena.olech@intel.com>", "Subject": "[PATCH v4 04/18] common/idpf/base: initial PTP support", "Date": "Mon, 18 Sep 2023 10:11:16 +0800", "Message-Id": "<20230918021130.192982-5-simei.su@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230918021130.192982-1-simei.su@intel.com>", "References": "<20230915021730.2681882-1-simei.su@intel.com>\n <20230918021130.192982-1-simei.su@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding a few PTP capabilities to determine which PTP features are\nenabled - legacy cross time, ptm, device clock control, PTP Tx\ntimestamp with direct registers access, PTP Tx timestamp using\nvirtchnl messages.\n\nCreating structures and opcodes to support feautres introduced by\ncapabilities.\n\nSigned-off-by: Milena Olech <milena.olech@intel.com>\nSigned-off-by: Simei Su <simei.su@intel.com>\nAcked-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/base/virtchnl2.h | 145 +++++++++++++++++++++++++++\n 1 file changed, 145 insertions(+)", "diff": "diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h\nindex c49e4b943c..320430df6f 100644\n--- a/drivers/common/idpf/base/virtchnl2.h\n+++ b/drivers/common/idpf/base/virtchnl2.h\n@@ -98,6 +98,9 @@\n #define\t\tVIRTCHNL2_OP_ADD_QUEUE_GROUPS\t\t538\n #define\t\tVIRTCHNL2_OP_DEL_QUEUE_GROUPS\t\t539\n #define\t\tVIRTCHNL2_OP_GET_PORT_STATS\t\t540\n+\t/* TimeSync opcodes */\n+#define\t\tVIRTCHNL2_OP_GET_PTP_CAPS\t\t541\n+#define\t\tVIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES\t542\n \n #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX\t0xFFFF\n \n@@ -1395,6 +1398,112 @@ struct virtchnl2_promisc_info {\n \n VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_promisc_info);\n \n+/* VIRTCHNL2_PTP_CAPS\n+ * PTP capabilities\n+ */\n+#define VIRTCHNL2_PTP_CAP_LEGACY_CROSS_TIME\tBIT(0)\n+#define VIRTCHNL2_PTP_CAP_PTM\t\t\tBIT(1)\n+#define VIRTCHNL2_PTP_CAP_DEVICE_CLOCK_CONTROL\tBIT(2)\n+#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_DIRECT\tBIT(3)\n+#define\tVIRTCHNL2_PTP_CAP_TX_TSTAMPS_VIRTCHNL\tBIT(4)\n+\n+/* Legacy cross time registers offsets */\n+struct virtchnl2_ptp_legacy_cross_time_reg {\n+\t__le32 shadow_time_0;\n+\t__le32 shadow_time_l;\n+\t__le32 shadow_time_h;\n+\t__le32 cmd_sync;\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_legacy_cross_time_reg);\n+\n+/* PTM cross time registers offsets */\n+struct virtchnl2_ptp_ptm_cross_time_reg {\n+\t__le32 art_l;\n+\t__le32 art_h;\n+\t__le32 cmd_sync;\n+\tu8 pad[4];\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_ptm_cross_time_reg);\n+\n+/* Registers needed to control the main clock */\n+struct virtchnl2_ptp_device_clock_control {\n+\t__le32 cmd;\n+\t__le32 incval_l;\n+\t__le32 incval_h;\n+\t__le32 shadj_l;\n+\t__le32 shadj_h;\n+\tu8 pad[4];\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_device_clock_control);\n+\n+/* Structure that defines tx tstamp entry - index and register offset */\n+struct virtchnl2_ptp_tx_tstamp_entry {\n+\t__le32 tx_latch_register_base;\n+\t__le32 tx_latch_register_offset;\n+\tu8 index;\n+\tu8 pad[7];\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_entry);\n+\n+/* Structure that defines tx tstamp entries - total number of latches\n+ * and the array of entries.\n+ */\n+struct virtchnl2_ptp_tx_tstamp {\n+\t__le16 num_latches;\n+\t/* latch size expressed in bits */\n+\t__le16 latch_size;\n+\tu8 pad[4];\n+\tstruct virtchnl2_ptp_tx_tstamp_entry ptp_tx_tstamp_entries[1];\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp);\n+\n+/* VIRTCHNL2_OP_GET_PTP_CAPS\n+ * PV/VF sends this message to negotiate PTP capabilities. CP updates bitmap\n+ * with supported features and fulfills appropriate structures.\n+ */\n+struct virtchnl2_get_ptp_caps {\n+\t/* PTP capability bitmap */\n+\t/* see VIRTCHNL2_PTP_CAPS definitions */\n+\t__le32 ptp_caps;\n+\tu8 pad[4];\n+\n+\tstruct virtchnl2_ptp_legacy_cross_time_reg legacy_cross_time_reg;\n+\tstruct virtchnl2_ptp_ptm_cross_time_reg ptm_cross_time_reg;\n+\tstruct virtchnl2_ptp_device_clock_control device_clock_control;\n+\tstruct virtchnl2_ptp_tx_tstamp tx_tstamp;\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(88, virtchnl2_get_ptp_caps);\n+\n+/* Structure that describes tx tstamp values, index and validity */\n+struct virtchnl2_ptp_tx_tstamp_latch {\n+\t__le32 tstamp_h;\n+\t__le32 tstamp_l;\n+\tu8 index;\n+\tu8 valid;\n+\tu8 pad[6];\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_latch);\n+\n+/* VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES\n+ * PF/VF sends this message to receive a specified number of timestamps\n+ * entries.\n+ */\n+struct virtchnl2_ptp_tx_tstamp_latches {\n+\t__le16 num_latches;\n+\t/* latch size expressed in bits */\n+\t__le16 latch_size;\n+\tu8 pad[4];\n+\tstruct virtchnl2_ptp_tx_tstamp_latch tstamp_latches[1];\n+};\n+\n+VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp_latches);\n \n static inline const char *virtchnl2_op_str(__le32 v_opcode)\n {\n@@ -1463,6 +1572,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode)\n \t\treturn \"VIRTCHNL2_OP_DEL_QUEUE_GROUPS\";\n \tcase VIRTCHNL2_OP_GET_PORT_STATS:\n \t\treturn \"VIRTCHNL2_OP_GET_PORT_STATS\";\n+\tcase VIRTCHNL2_OP_GET_PTP_CAPS:\n+\t\treturn \"VIRTCHNL2_OP_GET_PTP_CAPS\";\n+\tcase VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES:\n+\t\treturn \"VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES\";\n \tdefault:\n \t\treturn \"Unsupported (update virtchnl2.h)\";\n \t}\n@@ -1732,6 +1845,38 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3\n \t\tbreak;\n \tcase VIRTCHNL2_OP_RESET_VF:\n \t\tbreak;\n+\tcase VIRTCHNL2_OP_GET_PTP_CAPS:\n+\t\tvalid_len = sizeof(struct virtchnl2_get_ptp_caps);\n+\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl2_get_ptp_caps *ptp_caps =\n+\t\t\t(struct virtchnl2_get_ptp_caps *)msg;\n+\n+\t\t\tif (ptp_caps->tx_tstamp.num_latches == 0) {\n+\t\t\t\terr_msg_format = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tvalid_len += ((ptp_caps->tx_tstamp.num_latches - 1) *\n+\t\t\t\t sizeof(struct virtchnl2_ptp_tx_tstamp_entry));\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES:\n+\t\tvalid_len = sizeof(struct virtchnl2_ptp_tx_tstamp_latches);\n+\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl2_ptp_tx_tstamp_latches *tx_tstamp_latches =\n+\t\t\t(struct virtchnl2_ptp_tx_tstamp_latches *)msg;\n+\n+\t\t\tif (tx_tstamp_latches->num_latches == 0) {\n+\t\t\t\terr_msg_format = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tvalid_len += ((tx_tstamp_latches->num_latches - 1) *\n+\t\t\t\t sizeof(struct virtchnl2_ptp_tx_tstamp_latch));\n+\t\t}\n+\t\tbreak;\n \t/* These are always errors coming from the VF. */\n \tcase VIRTCHNL2_OP_EVENT:\n \tcase VIRTCHNL2_OP_UNKNOWN:\n", "prefixes": [ "v4", "04/18" ] }{ "id": 131520, "url": "