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{
    "id": 131368,
    "url": "http://patches.dpdk.org/api/patches/131368/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230912173039.1612287-10-beilei.xing@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230912173039.1612287-10-beilei.xing@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230912173039.1612287-10-beilei.xing@intel.com",
    "date": "2023-09-12T17:30:38",
    "name": "[v6,09/10] net/cpfl: create port representor",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "a3eeda16d090dc3331f7b70d1139b2af16bb6e4f",
    "submitter": {
        "id": 410,
        "url": "http://patches.dpdk.org/api/people/410/?format=api",
        "name": "Xing, Beilei",
        "email": "beilei.xing@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230912173039.1612287-10-beilei.xing@intel.com/mbox/",
    "series": [
        {
            "id": 29486,
            "url": "http://patches.dpdk.org/api/series/29486/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29486",
            "date": "2023-09-12T17:30:29",
            "name": "net/cpfl: support port representor",
            "version": 6,
            "mbox": "http://patches.dpdk.org/series/29486/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/131368/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/131368/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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            "from dpdk-beileix-icelake.sh.intel.com ([10.67.116.248])\n by fmsmga008.fm.intel.com with ESMTP; 12 Sep 2023 02:12:16 -0700"
        ],
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        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10830\"; a=\"375652088\"",
            "E=Sophos;i=\"6.02,245,1688454000\"; d=\"scan'208\";a=\"375652088\"",
            "E=McAfee;i=\"6600,9927,10830\"; a=\"809164459\"",
            "E=Sophos;i=\"6.02,245,1688454000\"; d=\"scan'208\";a=\"809164459\""
        ],
        "X-ExtLoop1": "1",
        "From": "beilei.xing@intel.com",
        "To": "jingjing.wu@intel.com",
        "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>,\n Qi Zhang <qi.z.zhang@intel.com>",
        "Subject": "[PATCH v6 09/10] net/cpfl: create port representor",
        "Date": "Tue, 12 Sep 2023 17:30:38 +0000",
        "Message-Id": "<20230912173039.1612287-10-beilei.xing@intel.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20230912173039.1612287-1-beilei.xing@intel.com>",
        "References": "<20230912162640.1439383-1-beilei.xing@intel.com>\n <20230912173039.1612287-1-beilei.xing@intel.com>",
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        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nTrack representor request in the allowlist.\nRepresentor will only be created for active vport.\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c      | 109 +++---\n drivers/net/cpfl/cpfl_ethdev.h      |  37 ++\n drivers/net/cpfl/cpfl_representor.c | 581 ++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_representor.h |  26 ++\n drivers/net/cpfl/meson.build        |   1 +\n 5 files changed, 710 insertions(+), 44 deletions(-)\n create mode 100644 drivers/net/cpfl/cpfl_representor.c\n create mode 100644 drivers/net/cpfl/cpfl_representor.h",
    "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 428d87b960..189072ab33 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -1645,7 +1645,7 @@ cpfl_handle_vchnl_event_msg(struct cpfl_adapter_ext *adapter, uint8_t *msg, uint\n \t}\n }\n \n-static int\n+int\n cpfl_vport_info_create(struct cpfl_adapter_ext *adapter,\n \t\t       struct cpfl_vport_id *vport_identity,\n \t\t       struct cpchnl2_event_vport_created *vport_created)\n@@ -1898,6 +1898,42 @@ cpfl_vport_map_uninit(struct cpfl_adapter_ext *adapter)\n \trte_hash_free(adapter->vport_map_hash);\n }\n \n+static int\n+cpfl_repr_allowlist_init(struct cpfl_adapter_ext *adapter)\n+{\n+\tchar hname[32];\n+\n+\tsnprintf(hname, 32, \"%s-repr_al\", adapter->name);\n+\n+\trte_spinlock_init(&adapter->repr_lock);\n+\n+#define CPFL_REPR_HASH_ENTRY_NUM 2048\n+\n+\tstruct rte_hash_parameters params = {\n+\t\t.name = hname,\n+\t\t.entries = CPFL_REPR_HASH_ENTRY_NUM,\n+\t\t.key_len = sizeof(struct cpfl_repr_id),\n+\t\t.hash_func = rte_hash_crc,\n+\t\t.socket_id = SOCKET_ID_ANY,\n+\t};\n+\n+\tadapter->repr_allowlist_hash = rte_hash_create(&params);\n+\n+\tif (adapter->repr_allowlist_hash == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to create repr allowlist hash\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+cpfl_repr_allowlist_uninit(struct cpfl_adapter_ext *adapter)\n+{\n+\trte_hash_free(adapter->repr_allowlist_hash);\n+}\n+\n+\n static int\n cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)\n {\n@@ -1928,6 +1964,12 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a\n \t\tgoto err_vport_map_init;\n \t}\n \n+\tret = cpfl_repr_allowlist_init(adapter);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init representor allowlist\");\n+\t\tgoto err_repr_allowlist_init;\n+\t}\n+\n \trte_eal_alarm_set(CPFL_ALARM_INTERVAL, cpfl_dev_alarm_handler, adapter);\n \n \tadapter->max_vport_nb = adapter->base.caps.max_vports > CPFL_MAX_VPORT_NUM ?\n@@ -1952,6 +1994,8 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a\n \n err_vports_alloc:\n \trte_eal_alarm_cancel(cpfl_dev_alarm_handler, adapter);\n+\tcpfl_repr_allowlist_uninit(adapter);\n+err_repr_allowlist_init:\n \tcpfl_vport_map_uninit(adapter);\n err_vport_map_init:\n \tidpf_adapter_deinit(base);\n@@ -2227,48 +2271,6 @@ cpfl_vport_devargs_process(struct cpfl_adapter_ext *adapter)\n \treturn 0;\n }\n \n-static int\n-cpfl_repr_devargs_process(struct cpfl_adapter_ext *adapter)\n-{\n-\tstruct cpfl_devargs *devargs = &adapter->devargs;\n-\tint i, j;\n-\n-\t/* check and refine repr args */\n-\tfor (i = 0; i < devargs->repr_args_num; i++) {\n-\t\tstruct rte_eth_devargs *eth_da = &devargs->repr_args[i];\n-\n-\t\t/* set default host_id to xeon host */\n-\t\tif (eth_da->nb_mh_controllers == 0) {\n-\t\t\teth_da->nb_mh_controllers = 1;\n-\t\t\teth_da->mh_controllers[0] = CPFL_HOST_ID_HOST;\n-\t\t} else {\n-\t\t\tfor (j = 0; j < eth_da->nb_mh_controllers; j++) {\n-\t\t\t\tif (eth_da->mh_controllers[j] > CPFL_HOST_ID_ACC) {\n-\t\t\t\t\tPMD_INIT_LOG(ERR, \"Invalid Host ID %d\",\n-\t\t\t\t\t\t     eth_da->mh_controllers[j]);\n-\t\t\t\t\treturn -EINVAL;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\n-\t\t/* set default pf to APF */\n-\t\tif (eth_da->nb_ports == 0) {\n-\t\t\teth_da->nb_ports = 1;\n-\t\t\teth_da->ports[0] = CPFL_PF_TYPE_APF;\n-\t\t} else {\n-\t\t\tfor (j = 0; j < eth_da->nb_ports; j++) {\n-\t\t\t\tif (eth_da->ports[j] > CPFL_PF_TYPE_CPF) {\n-\t\t\t\t\tPMD_INIT_LOG(ERR, \"Invalid Host ID %d\",\n-\t\t\t\t\t\t     eth_da->ports[j]);\n-\t\t\t\t\treturn -EINVAL;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n static int\n cpfl_vport_create(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)\n {\n@@ -2304,6 +2306,7 @@ cpfl_pci_probe_first(struct rte_pci_device *pci_dev)\n {\n \tstruct cpfl_adapter_ext *adapter;\n \tint retval;\n+\tuint16_t port_id;\n \n \tadapter = rte_zmalloc(\"cpfl_adapter_ext\",\n \t\t\t      sizeof(struct cpfl_adapter_ext), 0);\n@@ -2343,11 +2346,23 @@ cpfl_pci_probe_first(struct rte_pci_device *pci_dev)\n \tretval = cpfl_repr_devargs_process(adapter);\n \tif (retval != 0) {\n \t\tPMD_INIT_LOG(ERR, \"Failed to process repr devargs\");\n-\t\tgoto err;\n+\t\tgoto close_ethdev;\n \t}\n \n+\tretval = cpfl_repr_create(pci_dev, adapter);\n+\tif (retval != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to create representors \");\n+\t\tgoto close_ethdev;\n+\t}\n+\n+\n \treturn 0;\n \n+close_ethdev:\n+\t/* Ethdev created can be found RTE_ETH_FOREACH_DEV_OF through rte_device */\n+\tRTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {\n+\t\trte_eth_dev_close(port_id);\n+\t}\n err:\n \trte_spinlock_lock(&cpfl_adapter_lock);\n \tTAILQ_REMOVE(&cpfl_adapter_list, adapter, next);\n@@ -2374,6 +2389,12 @@ cpfl_pci_probe_again(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *ad\n \t\treturn ret;\n \t}\n \n+\tret = cpfl_repr_create(pci_dev, adapter);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to create representors \");\n+\t\treturn ret;\n+\t}\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nindex 362cad155d..a4ffd51fb3 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.h\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -21,6 +21,7 @@\n \n #include \"cpfl_logs.h\"\n #include \"cpfl_cpchnl.h\"\n+#include \"cpfl_representor.h\"\n \n /* Currently, backend supports up to 8 vports */\n #define CPFL_MAX_VPORT_NUM\t8\n@@ -60,11 +61,31 @@\n #define IDPF_DEV_ID_CPF\t\t\t0x1453\n #define VIRTCHNL2_QUEUE_GROUP_P2P\t0x100\n \n+#define CPFL_HOST_ID_NUM\t2\n+#define CPFL_PF_TYPE_NUM\t2\n #define CPFL_HOST_ID_HOST\t0\n #define CPFL_HOST_ID_ACC\t1\n #define CPFL_PF_TYPE_APF\t0\n #define CPFL_PF_TYPE_CPF\t1\n \n+/* Function IDs on IMC side */\n+#define CPFL_HOST0_APF\t\t0\n+#define CPFL_ACC_APF_ID\t\t4\n+#define CPFL_HOST0_CPF_ID\t8\n+#define CPFL_ACC_CPF_ID\t\t12\n+\n+#define CPFL_VPORT_LAN_PF\t0\n+#define CPFL_VPORT_LAN_VF\t1\n+\n+/* bit[15:14] type\n+ * bit[13] host/accelerator core\n+ * bit[12] apf/cpf\n+ * bit[11:0] vf\n+ */\n+#define CPFL_REPRESENTOR_ID(type, host_id, pf_id, vf_id)\t\\\n+\t((((type) & 0x3) << 14) + (((host_id) & 0x1) << 13) +\t\\\n+\t (((pf_id) & 0x1) << 12) + ((vf_id) & 0xfff))\n+\n struct cpfl_vport_param {\n \tstruct cpfl_adapter_ext *adapter;\n \tuint16_t devarg_id; /* arg id from user */\n@@ -110,6 +131,7 @@ struct cpfl_vport_info {\n \n enum cpfl_itf_type {\n \tCPFL_ITF_TYPE_VPORT,\n+\tCPFL_ITF_TYPE_REPRESENTOR,\n };\n \n struct cpfl_itf {\n@@ -135,6 +157,13 @@ struct cpfl_vport {\n \tbool p2p_manual_bind;\n };\n \n+struct cpfl_repr {\n+\tstruct cpfl_itf itf;\n+\tstruct cpfl_repr_id repr_id;\n+\tstruct rte_ether_addr mac_addr;\n+\tstruct cpfl_vport_info *vport_info;\n+};\n+\n struct cpfl_adapter_ext {\n \tTAILQ_ENTRY(cpfl_adapter_ext) next;\n \tstruct idpf_adapter base;\n@@ -152,10 +181,16 @@ struct cpfl_adapter_ext {\n \n \trte_spinlock_t vport_map_lock;\n \tstruct rte_hash *vport_map_hash;\n+\n+\trte_spinlock_t repr_lock;\n+\tstruct rte_hash *repr_allowlist_hash;\n };\n \n TAILQ_HEAD(cpfl_adapter_list, cpfl_adapter_ext);\n \n+int cpfl_vport_info_create(struct cpfl_adapter_ext *adapter,\n+\t\t\t   struct cpfl_vport_id *vport_identity,\n+\t\t\t   struct cpchnl2_event_vport_created *vport);\n int cpfl_cc_vport_list_get(struct cpfl_adapter_ext *adapter,\n \t\t\t   struct cpfl_vport_id *vi,\n \t\t\t   struct cpchnl2_get_vport_list_response *response);\n@@ -170,6 +205,8 @@ int cpfl_cc_vport_info_get(struct cpfl_adapter_ext *adapter,\n \tcontainer_of((p), struct cpfl_adapter_ext, base)\n #define CPFL_DEV_TO_VPORT(dev)\t\t\t\t\t\\\n \t((struct cpfl_vport *)((dev)->data->dev_private))\n+#define CPFL_DEV_TO_REPR(dev)\t\t\t\t\t\\\n+\t((struct cpfl_repr *)((dev)->data->dev_private))\n #define CPFL_DEV_TO_ITF(dev)\t\t\t\t\\\n \t((struct cpfl_itf *)((dev)->data->dev_private))\n \ndiff --git a/drivers/net/cpfl/cpfl_representor.c b/drivers/net/cpfl/cpfl_representor.c\nnew file mode 100644\nindex 0000000000..d2558c39a8\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_representor.c\n@@ -0,0 +1,581 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#include \"cpfl_representor.h\"\n+#include \"cpfl_rxtx.h\"\n+\n+static int\n+cpfl_repr_allowlist_update(struct cpfl_adapter_ext *adapter,\n+\t\t\t   struct cpfl_repr_id *repr_id,\n+\t\t\t   struct rte_eth_dev *dev)\n+{\n+\tint ret;\n+\n+\tif (rte_hash_lookup(adapter->repr_allowlist_hash, repr_id) < 0)\n+\t\treturn -ENOENT;\n+\n+\tret = rte_hash_add_key_data(adapter->repr_allowlist_hash, repr_id, dev);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_repr_allowlist_add(struct cpfl_adapter_ext *adapter,\n+\t\t\tstruct cpfl_repr_id *repr_id)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&adapter->repr_lock);\n+\tif (rte_hash_lookup(adapter->repr_allowlist_hash, repr_id) >= 0) {\n+\t\tret = -EEXIST;\n+\t\tgoto err;\n+\t}\n+\n+\tret = rte_hash_add_key(adapter->repr_allowlist_hash, repr_id);\n+\tif (ret < 0)\n+\t\tgoto err;\n+\n+\trte_spinlock_unlock(&adapter->repr_lock);\n+\treturn 0;\n+err:\n+\trte_spinlock_unlock(&adapter->repr_lock);\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_repr_devargs_process_one(struct cpfl_adapter_ext *adapter,\n+\t\t\t      struct rte_eth_devargs *eth_da)\n+{\n+\tstruct cpfl_repr_id repr_id;\n+\tint ret, c, p, v;\n+\n+\tfor (c = 0; c < eth_da->nb_mh_controllers; c++) {\n+\t\tfor (p = 0; p < eth_da->nb_ports; p++) {\n+\t\t\trepr_id.type = eth_da->type;\n+\t\t\tif (eth_da->type == RTE_ETH_REPRESENTOR_PF) {\n+\t\t\t\trepr_id.host_id = eth_da->mh_controllers[c];\n+\t\t\t\trepr_id.pf_id = eth_da->ports[p];\n+\t\t\t\trepr_id.vf_id = 0;\n+\t\t\t\tret = cpfl_repr_allowlist_add(adapter, &repr_id);\n+\t\t\t\tif (ret == -EEXIST)\n+\t\t\t\t\tcontinue;\n+\t\t\t\tif (ret) {\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to add PF repr to allowlist, \"\n+\t\t\t\t\t\t\t \"host_id = %d, pf_id = %d.\",\n+\t\t\t\t\t\t    repr_id.host_id, repr_id.pf_id);\n+\t\t\t\t\treturn ret;\n+\t\t\t\t}\n+\t\t\t} else if (eth_da->type == RTE_ETH_REPRESENTOR_VF) {\n+\t\t\t\tfor (v = 0; v < eth_da->nb_representor_ports; v++) {\n+\t\t\t\t\trepr_id.host_id = eth_da->mh_controllers[c];\n+\t\t\t\t\trepr_id.pf_id = eth_da->ports[p];\n+\t\t\t\t\trepr_id.vf_id = eth_da->representor_ports[v];\n+\t\t\t\t\tret = cpfl_repr_allowlist_add(adapter, &repr_id);\n+\t\t\t\t\tif (ret == -EEXIST)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\tif (ret) {\n+\t\t\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to add VF repr to allowlist, \"\n+\t\t\t\t\t\t\t\t \"host_id = %d, pf_id = %d, vf_id = %d.\",\n+\t\t\t\t\t\t\t    repr_id.host_id,\n+\t\t\t\t\t\t\t    repr_id.pf_id,\n+\t\t\t\t\t\t\t    repr_id.vf_id);\n+\t\t\t\t\t\treturn ret;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+cpfl_repr_devargs_process(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct cpfl_devargs *devargs = &adapter->devargs;\n+\tint ret, i, j;\n+\n+\t/* check and refine repr args */\n+\tfor (i = 0; i < devargs->repr_args_num; i++) {\n+\t\tstruct rte_eth_devargs *eth_da = &devargs->repr_args[i];\n+\n+\t\t/* set default host_id to host */\n+\t\tif (eth_da->nb_mh_controllers == 0) {\n+\t\t\teth_da->nb_mh_controllers = 1;\n+\t\t\teth_da->mh_controllers[0] = CPFL_HOST_ID_HOST;\n+\t\t} else {\n+\t\t\tfor (j = 0; j < eth_da->nb_mh_controllers; j++) {\n+\t\t\t\tif (eth_da->mh_controllers[j] > CPFL_HOST_ID_ACC) {\n+\t\t\t\t\tPMD_INIT_LOG(ERR, \"Invalid Host ID %d\",\n+\t\t\t\t\t\t     eth_da->mh_controllers[j]);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* set default pf to APF */\n+\t\tif (eth_da->nb_ports == 0) {\n+\t\t\teth_da->nb_ports = 1;\n+\t\t\teth_da->ports[0] = CPFL_PF_TYPE_APF;\n+\t\t} else {\n+\t\t\tfor (j = 0; j < eth_da->nb_ports; j++) {\n+\t\t\t\tif (eth_da->ports[j] > CPFL_PF_TYPE_CPF) {\n+\t\t\t\t\tPMD_INIT_LOG(ERR, \"Invalid Host ID %d\",\n+\t\t\t\t\t\t     eth_da->ports[j]);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tret = cpfl_repr_devargs_process_one(adapter, eth_da);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_allowlist_del(struct cpfl_adapter_ext *adapter,\n+\t\t\tstruct cpfl_repr_id *repr_id)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&adapter->repr_lock);\n+\n+\tret = rte_hash_del_key(adapter->repr_allowlist_hash, repr_id);\n+\tif (ret < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to delete repr from allowlist.\"\n+\t\t\t\t \"host_id = %d, type = %d, pf_id = %d, vf_id = %d\",\n+\t\t\t\t repr_id->host_id, repr_id->type,\n+\t\t\t\t repr_id->pf_id, repr_id->vf_id);\n+\t\tgoto err;\n+\t}\n+\n+\trte_spinlock_unlock(&adapter->repr_lock);\n+\treturn 0;\n+err:\n+\trte_spinlock_unlock(&adapter->repr_lock);\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_repr_uninit(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cpfl_repr *repr = CPFL_DEV_TO_REPR(eth_dev);\n+\tstruct cpfl_adapter_ext *adapter = repr->itf.adapter;\n+\n+\teth_dev->data->mac_addrs = NULL;\n+\n+\tcpfl_repr_allowlist_del(adapter, &repr->repr_id);\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_dev_configure(struct rte_eth_dev *dev)\n+{\n+\t/* now only 1 RX queue is supported */\n+\tif (dev->data->nb_rx_queues > 1)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_dev_close(struct rte_eth_dev *dev)\n+{\n+\treturn cpfl_repr_uninit(dev);\n+}\n+\n+static int\n+cpfl_repr_dev_info_get(struct rte_eth_dev *ethdev,\n+\t\t       struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct cpfl_repr *repr = CPFL_DEV_TO_REPR(ethdev);\n+\n+\tdev_info->device = ethdev->device;\n+\tdev_info->max_mac_addrs = 1;\n+\tdev_info->max_rx_queues = 1;\n+\tdev_info->max_tx_queues = 1;\n+\tdev_info->min_rx_bufsize = CPFL_MIN_BUF_SIZE;\n+\tdev_info->max_rx_pktlen = CPFL_MAX_FRAME_SIZE;\n+\n+\tdev_info->flow_type_rss_offloads = CPFL_RSS_OFFLOAD_ALL;\n+\n+\tdev_info->rx_offload_capa =\n+\t\tRTE_ETH_RX_OFFLOAD_VLAN_STRIP\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_QINQ_STRIP\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_IPV4_CKSUM\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_UDP_CKSUM\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_TCP_CKSUM\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM\t|\n+\t\tRTE_ETH_RX_OFFLOAD_SCATTER\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_VLAN_FILTER\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_RSS_HASH\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_TIMESTAMP;\n+\n+\tdev_info->tx_offload_capa =\n+\t\tRTE_ETH_TX_OFFLOAD_VLAN_INSERT\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_QINQ_INSERT\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_IPV4_CKSUM\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_UDP_CKSUM\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_TCP_CKSUM\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_SCTP_CKSUM\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM\t|\n+\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS\t\t|\n+\t\tRTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;\n+\n+\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n+\t\t.rx_free_thresh = CPFL_DEFAULT_RX_FREE_THRESH,\n+\t\t.rx_drop_en = 0,\n+\t\t.offloads = 0,\n+\t};\n+\n+\tdev_info->default_txconf = (struct rte_eth_txconf) {\n+\t\t.tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH,\n+\t\t.tx_rs_thresh = CPFL_DEFAULT_TX_RS_THRESH,\n+\t\t.offloads = 0,\n+\t};\n+\n+\tdev_info->rx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = CPFL_MAX_RING_DESC,\n+\t\t.nb_min = CPFL_MIN_RING_DESC,\n+\t\t.nb_align = CPFL_ALIGN_RING_DESC,\n+\t};\n+\n+\tdev_info->tx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = CPFL_MAX_RING_DESC,\n+\t\t.nb_min = CPFL_MIN_RING_DESC,\n+\t\t.nb_align = CPFL_ALIGN_RING_DESC,\n+\t};\n+\n+\tdev_info->switch_info.name = ethdev->device->name;\n+\tdev_info->switch_info.domain_id = 0; /* the same domain*/\n+\tdev_info->switch_info.port_id = repr->vport_info->vport.info.vsi_id;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_dev_start(struct rte_eth_dev *dev)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_dev_stop(struct rte_eth_dev *dev)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\tdev->data->dev_started = 0;\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_rx_queue_setup(__rte_unused struct rte_eth_dev *dev,\n+\t\t\t __rte_unused uint16_t queue_id,\n+\t\t\t __rte_unused uint16_t nb_desc,\n+\t\t\t __rte_unused unsigned int socket_id,\n+\t\t\t __rte_unused const struct rte_eth_rxconf *conf,\n+\t\t\t __rte_unused struct rte_mempool *pool)\n+{\n+\t/* Dummy */\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_repr_tx_queue_setup(__rte_unused struct rte_eth_dev *dev,\n+\t\t\t __rte_unused uint16_t queue_id,\n+\t\t\t __rte_unused uint16_t nb_desc,\n+\t\t\t __rte_unused unsigned int socket_id,\n+\t\t\t __rte_unused const struct rte_eth_txconf *conf)\n+{\n+\t/* Dummy */\n+\treturn 0;\n+}\n+\n+static const struct eth_dev_ops cpfl_repr_dev_ops = {\n+\t.dev_start\t\t= cpfl_repr_dev_start,\n+\t.dev_stop\t\t= cpfl_repr_dev_stop,\n+\t.dev_configure\t\t= cpfl_repr_dev_configure,\n+\t.dev_close\t\t= cpfl_repr_dev_close,\n+\t.dev_infos_get\t\t= cpfl_repr_dev_info_get,\n+\n+\t.rx_queue_setup\t\t= cpfl_repr_rx_queue_setup,\n+\t.tx_queue_setup\t\t= cpfl_repr_tx_queue_setup,\n+};\n+\n+static int\n+cpfl_repr_init(struct rte_eth_dev *eth_dev, void *init_param)\n+{\n+\tstruct cpfl_repr *repr = CPFL_DEV_TO_REPR(eth_dev);\n+\tstruct cpfl_repr_param *param = init_param;\n+\tstruct cpfl_adapter_ext *adapter = param->adapter;\n+\n+\trepr->repr_id = param->repr_id;\n+\trepr->vport_info = param->vport_info;\n+\trepr->itf.type = CPFL_ITF_TYPE_REPRESENTOR;\n+\trepr->itf.adapter = adapter;\n+\trepr->itf.data = eth_dev->data;\n+\n+\teth_dev->dev_ops = &cpfl_repr_dev_ops;\n+\n+\teth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;\n+\n+\teth_dev->data->representor_id =\n+\t\tCPFL_REPRESENTOR_ID(repr->repr_id.type,\n+\t\t\t\t    repr->repr_id.host_id,\n+\t\t\t\t    repr->repr_id.pf_id,\n+\t\t\t\t    repr->repr_id.vf_id);\n+\n+\teth_dev->data->mac_addrs = &repr->mac_addr;\n+\n+\trte_eth_random_addr(repr->mac_addr.addr_bytes);\n+\n+\treturn cpfl_repr_allowlist_update(adapter, &repr->repr_id, eth_dev);\n+}\n+\n+static int\n+cpfl_func_id_get(uint8_t host_id, uint8_t pf_id)\n+{\n+\tif ((host_id != CPFL_HOST_ID_HOST &&\n+\t     host_id != CPFL_HOST_ID_ACC) ||\n+\t    (pf_id != CPFL_PF_TYPE_APF &&\n+\t     pf_id != CPFL_PF_TYPE_CPF))\n+\t\treturn -EINVAL;\n+\n+\tstatic const uint32_t func_id_map[CPFL_HOST_ID_NUM][CPFL_PF_TYPE_NUM] = {\n+\t\t[CPFL_HOST_ID_HOST][CPFL_PF_TYPE_APF] = CPFL_HOST0_APF,\n+\t\t[CPFL_HOST_ID_HOST][CPFL_PF_TYPE_CPF] = CPFL_HOST0_CPF_ID,\n+\t\t[CPFL_HOST_ID_ACC][CPFL_PF_TYPE_APF] = CPFL_ACC_APF_ID,\n+\t\t[CPFL_HOST_ID_ACC][CPFL_PF_TYPE_CPF] = CPFL_ACC_CPF_ID,\n+\t};\n+\n+\treturn func_id_map[host_id][pf_id];\n+}\n+\n+static bool\n+cpfl_match_repr_with_vport(const struct cpfl_repr_id *repr_id,\n+\t\t\t   struct cpchnl2_vport_info *info)\n+{\n+\tint func_id;\n+\n+\tif (repr_id->type == RTE_ETH_REPRESENTOR_PF &&\n+\t    info->func_type == CPFL_VPORT_LAN_PF) {\n+\t\tfunc_id = cpfl_func_id_get(repr_id->host_id, repr_id->pf_id);\n+\t\tif (func_id < 0 || func_id != info->pf_id)\n+\t\t\treturn false;\n+\t\telse\n+\t\t\treturn true;\n+\t} else if (repr_id->type == RTE_ETH_REPRESENTOR_VF &&\n+\t\t   info->func_type == CPFL_VPORT_LAN_VF) {\n+\t\tif (repr_id->vf_id == info->vf_id)\n+\t\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+static int\n+cpfl_repr_vport_list_query(struct cpfl_adapter_ext *adapter,\n+\t\t\t   const struct cpfl_repr_id *repr_id,\n+\t\t\t   struct cpchnl2_get_vport_list_response *response)\n+{\n+\tstruct cpfl_vport_id vi;\n+\tint ret;\n+\n+\tif (repr_id->type == RTE_ETH_REPRESENTOR_PF) {\n+\t\t/* PF */\n+\t\tvi.func_type = CPCHNL2_FUNC_TYPE_PF;\n+\t\tvi.pf_id = cpfl_func_id_get(repr_id->host_id, repr_id->pf_id);\n+\t\tvi.vf_id = 0;\n+\t} else {\n+\t\t/* VF */\n+\t\tvi.func_type = CPCHNL2_FUNC_TYPE_SRIOV;\n+\t\tvi.pf_id = CPFL_HOST0_APF;\n+\t\tvi.vf_id = repr_id->vf_id;\n+\t}\n+\n+\tret = cpfl_cc_vport_list_get(adapter, &vi, response);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_repr_vport_info_query(struct cpfl_adapter_ext *adapter,\n+\t\t\t   const struct cpfl_repr_id *repr_id,\n+\t\t\t   struct cpchnl2_vport_id *vport_id,\n+\t\t\t   struct cpchnl2_get_vport_info_response *response)\n+{\n+\tstruct cpfl_vport_id vi;\n+\tint ret;\n+\n+\tif (repr_id->type == RTE_ETH_REPRESENTOR_PF) {\n+\t\t/* PF */\n+\t\tvi.func_type = CPCHNL2_FUNC_TYPE_PF;\n+\t\tvi.pf_id = cpfl_func_id_get(repr_id->host_id, repr_id->pf_id);\n+\t\tvi.vf_id = 0;\n+\t} else {\n+\t\t/* VF */\n+\t\tvi.func_type = CPCHNL2_FUNC_TYPE_SRIOV;\n+\t\tvi.pf_id = CPFL_HOST0_APF;\n+\t\tvi.vf_id = repr_id->vf_id;\n+\t}\n+\n+\tret = cpfl_cc_vport_info_get(adapter, vport_id, &vi, response);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_repr_vport_map_update(struct cpfl_adapter_ext *adapter,\n+\t\t\t   const struct cpfl_repr_id *repr_id, uint32_t vport_id,\n+\t\t\t   struct cpchnl2_get_vport_info_response *response)\n+{\n+\tstruct cpfl_vport_id vi;\n+\tint ret;\n+\n+\tvi.vport_id = vport_id;\n+\tif (repr_id->type == RTE_ETH_REPRESENTOR_PF) {\n+\t\t/* PF */\n+\t\tvi.func_type = CPCHNL2_FUNC_TYPE_PF;\n+\t\tvi.pf_id = cpfl_func_id_get(repr_id->host_id, repr_id->pf_id);\n+\t} else {\n+\t\t/* VF */\n+\t\tvi.func_type = CPCHNL2_FUNC_TYPE_SRIOV;\n+\t\tvi.pf_id = CPFL_HOST0_APF;\n+\t\tvi.vf_id = repr_id->vf_id;\n+\t}\n+\n+\tret = cpfl_vport_info_create(adapter, &vi, (struct cpchnl2_event_vport_created *)response);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Fail to update vport map hash for representor.\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+cpfl_repr_create(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct rte_eth_dev *dev;\n+\tuint32_t iter = 0;\n+\tconst struct cpfl_repr_id *repr_id;\n+\tconst struct cpfl_vport_id *vp_id;\n+\tstruct cpchnl2_get_vport_list_response *vlist_resp;\n+\tstruct cpchnl2_get_vport_info_response vinfo_resp;\n+\tint ret;\n+\n+\tvlist_resp = rte_zmalloc(NULL, IDPF_DFLT_MBX_BUF_SIZE, 0);\n+\tif (vlist_resp == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trte_spinlock_lock(&adapter->repr_lock);\n+\n+\twhile (rte_hash_iterate(adapter->repr_allowlist_hash,\n+\t\t\t\t(const void **)&repr_id, (void **)&dev, &iter) >= 0) {\n+\t\tstruct cpfl_vport_info *vi;\n+\t\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\t\tuint32_t iter_iter = 0;\n+\t\tint i;\n+\n+\t\t/* skip representor already be created */\n+\t\tif (dev != NULL)\n+\t\t\tcontinue;\n+\n+\t\tif (repr_id->type == RTE_ETH_REPRESENTOR_VF)\n+\t\t\tsnprintf(name, sizeof(name), \"net_%s_representor_c%dpf%dvf%d\",\n+\t\t\t\t pci_dev->name,\n+\t\t\t\t repr_id->host_id,\n+\t\t\t\t repr_id->pf_id,\n+\t\t\t\t repr_id->vf_id);\n+\t\telse\n+\t\t\tsnprintf(name, sizeof(name), \"net_%s_representor_c%dpf%d\",\n+\t\t\t\t pci_dev->name,\n+\t\t\t\t repr_id->host_id,\n+\t\t\t\t repr_id->pf_id);\n+\n+\t\t/* get vport list for the port representor */\n+\t\tret = cpfl_repr_vport_list_query(adapter, repr_id, vlist_resp);\n+\t\tif (ret != 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to get host%d pf%d vf%d's vport list\",\n+\t\t\t\t     repr_id->host_id, repr_id->pf_id, repr_id->vf_id);\n+\t\t\tgoto err;\n+\t\t}\n+\n+\t\tif (vlist_resp->nof_vports == 0) {\n+\t\t\tPMD_INIT_LOG(WARNING, \"No matched vport for representor %s\", name);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* get all vport info for the port representor */\n+\t\tfor (i = 0; i < vlist_resp->nof_vports; i++) {\n+\t\t\tret = cpfl_repr_vport_info_query(adapter, repr_id,\n+\t\t\t\t\t\t\t &vlist_resp->vports[i], &vinfo_resp);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tPMD_INIT_LOG(ERR, \"Failed to get host%d pf%d vf%d vport[%d]'s info\",\n+\t\t\t\t\t     repr_id->host_id, repr_id->pf_id, repr_id->vf_id,\n+\t\t\t\t\t     vlist_resp->vports[i].vport_id);\n+\t\t\t\tgoto err;\n+\t\t\t}\n+\n+\t\t\tret = cpfl_repr_vport_map_update(adapter, repr_id,\n+\t\t\t\t\t\t vlist_resp->vports[i].vport_id, &vinfo_resp);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tPMD_INIT_LOG(ERR, \"Failed to update  host%d pf%d vf%d vport[%d]'s info to vport_map_hash\",\n+\t\t\t\t\t     repr_id->host_id, repr_id->pf_id, repr_id->vf_id,\n+\t\t\t\t\t     vlist_resp->vports[i].vport_id);\n+\t\t\t\tgoto err;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* find the matched vport */\n+\t\trte_spinlock_lock(&adapter->vport_map_lock);\n+\n+\t\twhile (rte_hash_iterate(adapter->vport_map_hash,\n+\t\t\t\t\t(const void **)&vp_id, (void **)&vi, &iter_iter) >= 0) {\n+\t\t\tstruct cpfl_repr_param param;\n+\n+\t\t\tif (!cpfl_match_repr_with_vport(repr_id, &vi->vport.info))\n+\t\t\t\tcontinue;\n+\n+\t\t\tparam.adapter = adapter;\n+\t\t\tparam.repr_id = *repr_id;\n+\t\t\tparam.vport_info = vi;\n+\n+\t\t\tret = rte_eth_dev_create(&pci_dev->device,\n+\t\t\t\t\t\t name,\n+\t\t\t\t\t\t sizeof(struct cpfl_repr),\n+\t\t\t\t\t\t NULL, NULL, cpfl_repr_init,\n+\t\t\t\t\t\t &param);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tPMD_INIT_LOG(ERR, \"Failed to create representor %s\", name);\n+\t\t\t\trte_spinlock_unlock(&adapter->vport_map_lock);\n+\t\t\t\tgoto err;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\trte_spinlock_unlock(&adapter->vport_map_lock);\n+\t}\n+\n+err:\n+\trte_spinlock_unlock(&adapter->repr_lock);\n+\trte_free(vlist_resp);\n+\treturn ret;\n+}\ndiff --git a/drivers/net/cpfl/cpfl_representor.h b/drivers/net/cpfl/cpfl_representor.h\nnew file mode 100644\nindex 0000000000..d3a4de531e\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_representor.h\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_REPRESENTOR_H_\n+#define _CPFL_REPRESENTOR_H_\n+\n+#include <ethdev_pci.h>\n+#include <rte_ethdev.h>\n+\n+struct cpfl_repr_id {\n+\tuint8_t host_id;\n+\tuint8_t pf_id;\n+\tuint8_t type;\n+\tuint8_t vf_id;\n+};\n+\n+struct cpfl_repr_param {\n+\tstruct cpfl_adapter_ext *adapter;\n+\tstruct cpfl_repr_id repr_id;\n+\tstruct cpfl_vport_info *vport_info;\n+};\n+\n+int cpfl_repr_devargs_process(struct cpfl_adapter_ext *adapter);\n+int cpfl_repr_create(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter);\n+#endif\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nindex 2f0f5d8434..d8b92ae16a 100644\n--- a/drivers/net/cpfl/meson.build\n+++ b/drivers/net/cpfl/meson.build\n@@ -17,6 +17,7 @@ sources = files(\n         'cpfl_ethdev.c',\n         'cpfl_rxtx.c',\n         'cpfl_vchnl.c',\n+        'cpfl_representor.c',\n )\n \n if arch_subdir == 'x86'\n",
    "prefixes": [
        "v6",
        "09/10"
    ]
}