get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/129133/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 129133,
    "url": "http://patches.dpdk.org/api/patches/129133/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230630062847.432448-1-bingz@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230630062847.432448-1-bingz@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230630062847.432448-1-bingz@nvidia.com",
    "date": "2023-06-30T06:28:47",
    "name": "[3/7] net/mlx5: fix the error set in Tx representor tagging",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c8a0c4dc0a302b2de7b4a4bc16eb4d49e457fad2",
    "submitter": {
        "id": 1976,
        "url": "http://patches.dpdk.org/api/people/1976/?format=api",
        "name": "Bing Zhao",
        "email": "bingz@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230630062847.432448-1-bingz@nvidia.com/mbox/",
    "series": [
        {
            "id": 28725,
            "url": "http://patches.dpdk.org/api/series/28725/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28725",
            "date": "2023-06-30T06:28:47",
            "name": null,
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/28725/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/129133/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/129133/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E0D6442D73;\n\tFri, 30 Jun 2023 08:29:28 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6A8C2406B5;\n\tFri, 30 Jun 2023 08:29:28 +0200 (CEST)",
            "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2056.outbound.protection.outlook.com [40.107.237.56])\n by mails.dpdk.org (Postfix) with ESMTP id EA6334021F\n for <dev@dpdk.org>; Fri, 30 Jun 2023 08:29:26 +0200 (CEST)",
            "from BN9P223CA0004.NAMP223.PROD.OUTLOOK.COM (2603:10b6:408:10b::9)\n by SN7PR12MB7154.namprd12.prod.outlook.com (2603:10b6:806:2a5::16) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.37; Fri, 30 Jun\n 2023 06:29:24 +0000",
            "from BN8NAM11FT038.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:10b:cafe::6a) by BN9P223CA0004.outlook.office365.com\n (2603:10b6:408:10b::9) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.22 via Frontend\n Transport; Fri, 30 Jun 2023 06:29:24 +0000",
            "from mail.nvidia.com (216.228.117.160) by\n BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6500.49 via Frontend Transport; Fri, 30 Jun 2023 06:29:24 +0000",
            "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Thu, 29 Jun 2023\n 23:29:09 -0700",
            "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 29 Jun\n 2023 23:29:06 -0700"
        ],
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=nVH4oS9AZ7oTCBPkDCaKEbKutMChQNl18VsvH+r1mURP2/pKwSQiZdYoy2Urj284/qeBL3yTt3w5+WHS3M28ah7xebzyk9R7QWTSLOlBdb5mF8es2BAsauA6Q5gMwJ+iSBzMp3LplPslgIJVx171SPNZTUNhz9Azr7IM/wWHZ57PsDgTE5IZ23J8aw0pD5XJ6Us84ZzG/12r7YVi7qkrXZgmr2QOQKdhAx7W2mI02Z/oECLx7Y9p5hUTBTRG+D05O5dLW21YQgRtFzLAgyAQp6J2gJHXuoNX8Sqp8RYTr9t5fdBbgLV4ADRQv8qD+0ugOvVA3n40rddIp6wORtwqCg==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=hHY4JhMM7akhduRdJ7LCVbV05V1jnRcpLOQH5VkdYDM=;\n b=OD+I4keWWgaOoBWFuOebd0QrMUkStopAuM3QhfoctNnK6+8gCGBRMM2NYBt2HiIeRaOkTZNkHkGO8XVwYqgA1tQsKWyYORnHKl3QNwUlzkvBRolHpPq+ckP30+RUvwgzJ4igSfeEec68nsuRgy/d9bLQbLbMccgTuByiRKmPTc25p68YcLjkT3xx9iDj7kS+wk4gfHRMX+4ZDul/F81Z4oVVBOLvVPp+LQZRIqCc7lz1QjNWD3SL/5RPAaPQeyNT9gTsXHz7j1NdyyneCGtQgA6kKfTywwQ8qfUz1Dq1mjqIE4MbZNCVFWSo28s3XeRvnFM8aW2PqcF95xjOagyDxQ==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=hHY4JhMM7akhduRdJ7LCVbV05V1jnRcpLOQH5VkdYDM=;\n b=hwnNj530TTsttFpEufNVdPAgspPKy+F1nOUB+n4XWtxo+VYtbmj+nFp+Bf1zwc4tWv9m+gX1w3nSEPAzShzX11CaFkttDUZ/QYwht7ZlBr9sfkute5xZxLcQWljVbRzJwdOH7WVRrbCrjsT1YHLWVhr0ZGdyWQUREM0egawAk5KxN9WZ2e6gHDn1UOyBVNTAWHneMArxQnEQi5cjbA2/Tj6ek7I7ukxGyHoJbzPnLgAWqMMoQANc7Lwdw2JfABfdTgS0fKjw/wOyHgpnZAle9xxmZ1hzB2ILAqKoQvwujmaCD5ZGLUv8f0NS9ODbSRRUJBasbfqs+s0CZ+gYIst4zg==",
        "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;",
        "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C",
        "From": "Bing Zhao <bingz@nvidia.com>",
        "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <suanmingm@nvidia.com>, <rasland@nvidia.com>",
        "CC": "<dev@dpdk.org>, <dsosnowski@nvidia.com>",
        "Subject": "[PATCH 3/7] net/mlx5: fix the error set in Tx representor tagging",
        "Date": "Fri, 30 Jun 2023 09:28:47 +0300",
        "Message-ID": "<20230630062847.432448-1-bingz@nvidia.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.126.230.35]",
        "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)",
        "X-EOPAttributedMessage": "0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT038:EE_|SN7PR12MB7154:EE_",
        "X-MS-Office365-Filtering-Correlation-Id": "e4100f31-04f5-4c2f-9680-08db793358e2",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "BCL:0;",
        "X-Microsoft-Antispam-Message-Info": "\n apv13ve47u6+qm3YDNEaDocC0scnwYvZT6FFgUdbvTfMm2OWGlvfMxCqkpZl5c4u5gUSwwur+TChhuE5Lj6uqNa6MjyIFxhoemqUDx1NV9oGOAXKtJff+lU2+zdF9VzzbfcKyYweAC5nuB3mn7yr/hy7Y7jzm3EL7/RKq2Va5C/Td33+bwYjKpKgS/yZPYlBG8dN/+zIemE38r2mTZ0bYjBjNFA+4ak0WZSXjEwbSV1XxpSBNdPN1xI4m3dlUkwCnGWBpCYqi+XFw2VRaOf3FVeKyzFUaOjfQxv/clz1LlWgRRWD+lkRbiv5X/ja42d4PTqhtPBP6xKGBTXjza6mfQpmyCIr8ogp83hFtYpVetVsT+YSdhqona60nArOvnlv6xIS0g9nFo5Gvs+UPDQUtT1AcmKi61A7POQI88lzxbwsnMy8WtN7M6Wbb9ejZT8d9TFuzexPDcKaeXnK/TWL56Xptv6/zewW/2LzIKgknwP1cBJRfz0uvJ8v9ZZPkfeuEPPQ7dATYIXQooujoo+ZjCWz4WR2vIyaEOux+yJo94+nvMBXgVeDMxl/EXCX0JUD4CS86++HjCrhiIteIk40Uu4YUvA0DJWw9bkxDsEOhmG0xFZFiHOEr36Kn6jvz34GlyvzOiIpg7EZYPNRp70/4VyIH7+D9UceZrs8DG8leob22JLg3Pg2oQzIolJCLP/oK8Wgd1uwywvq7pLO6QKroYevAUEUcbR6x3AmDnqcY3ybjqSFd3UgAv7ONKXdTJ6s",
        "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199021)(36840700001)(40470700004)(46966006)(107886003)(5660300002)(8676002)(7696005)(8936002)(41300700001)(6286002)(186003)(2906002)(16526019)(40460700003)(2616005)(356005)(82310400005)(336012)(426003)(110136005)(36860700001)(54906003)(86362001)(478600001)(47076005)(83380400001)(40480700001)(6636002)(70206006)(316002)(70586007)(4326008)(1076003)(26005)(7636003)(82740400003)(6666004)(55016003)(36756003);\n DIR:OUT; SFP:1101;",
        "X-OriginatorOrg": "Nvidia.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jun 2023 06:29:24.2563 (UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e4100f31-04f5-4c2f-9680-08db793358e2",
        "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]",
        "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT038.eop-nam11.prod.protection.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7154",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "In the previous implementation, the error information was not set\nwhen there was a failure during the initialization.\n\nThe pointer from the user should be passed to the called functions\nto be set properly before returning.\n\nFixes: 483181f7b6dd (\"net/mlx5: support device control of representor matching\")\nCc: dsosnowski@nvidia.com\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 44 +++++++++++++++++++--------------\n 1 file changed, 25 insertions(+), 19 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex ba2f1f7c92..6683bcbc7f 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5961,12 +5961,14 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)\n  *\n  * @param dev\n  *   Pointer to Ethernet device.\n+ * @param[out] error\n+ *   Pointer to error structure.\n  *\n  * @return\n  *   Pointer to pattern template on success. NULL otherwise, and rte_errno is set.\n  */\n static struct rte_flow_pattern_template *\n-flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev)\n+flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)\n {\n \tstruct rte_flow_pattern_template_attr attr = {\n \t\t.relaxed_matching = 0,\n@@ -5985,7 +5987,7 @@ flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev)\n \t\t},\n \t};\n \n-\treturn flow_hw_pattern_template_create(dev, &attr, items, NULL);\n+\treturn flow_hw_pattern_template_create(dev, &attr, items, error);\n }\n \n static __rte_always_inline uint32_t\n@@ -6043,12 +6045,15 @@ flow_hw_update_action_mask(struct rte_flow_action *action,\n  *\n  * @param dev\n  *   Pointer to Ethernet device.\n+ * @param[out] error\n+ *   Pointer to error structure.\n  *\n  * @return\n  *   Pointer to actions template on success. NULL otherwise, and rte_errno is set.\n  */\n static struct rte_flow_actions_template *\n-flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev)\n+flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,\n+\t\t\t\t\t  struct rte_flow_error *error)\n {\n \tuint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);\n \tuint32_t tag_value = flow_hw_tx_tag_regc_value(dev);\n@@ -6137,7 +6142,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev)\n \t\t\t\t   NULL, NULL);\n \tidx++;\n \tMLX5_ASSERT(idx <= RTE_DIM(actions_v));\n-\treturn flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, NULL);\n+\treturn flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);\n }\n \n static void\n@@ -6166,12 +6171,14 @@ flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)\n  *\n  * @param dev\n  *   Pointer to Ethernet device.\n+ * @param[out] error\n+ *   Pointer to error structure.\n  *\n  * @return\n  *   0 on success, negative errno value otherwise.\n  */\n static int\n-flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev)\n+flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct rte_flow_template_table_attr attr = {\n@@ -6189,20 +6196,22 @@ flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev)\n \n \tMLX5_ASSERT(priv->sh->config.dv_esw_en);\n \tMLX5_ASSERT(priv->sh->config.repr_matching);\n-\tpriv->hw_tx_repr_tagging_pt = flow_hw_create_tx_repr_sq_pattern_tmpl(dev);\n+\tpriv->hw_tx_repr_tagging_pt =\n+\t\tflow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);\n \tif (!priv->hw_tx_repr_tagging_pt)\n-\t\tgoto error;\n-\tpriv->hw_tx_repr_tagging_at = flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev);\n+\t\tgoto err;\n+\tpriv->hw_tx_repr_tagging_at =\n+\t\tflow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);\n \tif (!priv->hw_tx_repr_tagging_at)\n-\t\tgoto error;\n+\t\tgoto err;\n \tpriv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,\n \t\t\t\t\t\t\t    &priv->hw_tx_repr_tagging_pt, 1,\n \t\t\t\t\t\t\t    &priv->hw_tx_repr_tagging_at, 1,\n-\t\t\t\t\t\t\t    NULL);\n+\t\t\t\t\t\t\t    error);\n \tif (!priv->hw_tx_repr_tagging_tbl)\n-\t\tgoto error;\n+\t\tgoto err;\n \treturn 0;\n-error:\n+err:\n \tflow_hw_cleanup_tx_repr_tagging(dev);\n \treturn -rte_errno;\n }\n@@ -7634,8 +7643,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tgoto err;\n \t}\n \n-\tmemcpy(_queue_attr, queue_attr,\n-\t       sizeof(void *) * nb_queue);\n+\tmemcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);\n \t_queue_attr[nb_queue] = &ctrl_queue_attr;\n \tpriv->acts_ipool = mlx5_ipool_create(&cfg);\n \tif (!priv->acts_ipool)\n@@ -7728,7 +7736,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tMLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));\n \t\tif (is_proxy) {\n \t\t\tDRV_LOG(ERR, \"cross vHCA shared mode not supported \"\n-\t\t\t\t     \" for E-Switch confgiurations\");\n+\t\t\t\t\"for E-Switch confgiurations\");\n \t\t\trte_errno = ENOTSUP;\n \t\t\tgoto err;\n \t\t}\n@@ -7815,11 +7823,9 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\tgoto err;\n \t}\n \tif (priv->sh->config.dv_esw_en && priv->sh->config.repr_matching) {\n-\t\tret = flow_hw_setup_tx_repr_tagging(dev);\n-\t\tif (ret) {\n-\t\t\trte_errno = -ret;\n+\t\tret = flow_hw_setup_tx_repr_tagging(dev, error);\n+\t\tif (ret)\n \t\t\tgoto err;\n-\t\t}\n \t}\n \tif (is_proxy) {\n \t\tret = flow_hw_create_vport_actions(priv);\n",
    "prefixes": [
        "3/7"
    ]
}