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GET /api/patches/128809/?format=api
{ "id": 128809, "url": "http://patches.dpdk.org/api/patches/128809/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230620012322.788099-7-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230620012322.788099-7-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230620012322.788099-7-suanmingm@nvidia.com", "date": "2023-06-20T01:23:19", "name": "[v3,6/9] common/mlx5: add WQE-based QP synchronous basics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "df54f45849e775a1b18a88f2b9f904056e040337", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230620012322.788099-7-suanmingm@nvidia.com/mbox/", "series": [ { "id": 28569, "url": "http://patches.dpdk.org/api/series/28569/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28569", "date": "2023-06-20T01:23:14", "name": "[v3,1/9] common/mlx5: export memory region lookup by address", "version": 3, "mbox": "http://patches.dpdk.org/series/28569/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/128809/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/128809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 04DD042CFF;\n\tTue, 20 Jun 2023 03:24:58 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 93AB942D3E;\n\tTue, 20 Jun 2023 03:24:39 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2079.outbound.protection.outlook.com [40.107.237.79])\n by mails.dpdk.org (Postfix) with ESMTP id 0FA3E42D12\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<rasland@nvidia.com>, <dev@dpdk.org>, <gakhil@marvell.com>", "Subject": "[PATCH v3 6/9] common/mlx5: add WQE-based QP synchronous basics", "Date": "Tue, 20 Jun 2023 04:23:19 +0300", "Message-ID": "<20230620012322.788099-7-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230620012322.788099-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>\n <20230620012322.788099-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF000252A3:EE_|MW4PR12MB6732:EE_", "X-MS-Office365-Filtering-Correlation-Id": "92ca5bf4-83f9-4fd1-4d50-08db712d1b9e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n zgWh/9GiMFqgrai+Xdh0b19zkPl6LGyoSxV+L21U73P+uDYF/WTdwpM5mUHZuXDe6OYuWZyEaBiXY92DvKXeGUKva1lz+CNBKP0CSVkTxdFqBBZE8PWEU4VAF5qA6rJN4hidpwpkncbPXDXtRi1S6b8XmY9h+TejVXzR2CkoSj5kCqPwDLiQfw7Q2+DPpzx+U+iN+Ogk3jYiWoumAOc2xAvUW0X4kT9/VEsI+b46LnDreRGGhEl6D2psk/Zm44oE6obs+chS2JCt3Qa8LbKH57XJetXt5LF+0djE85jsBwBIREwKTTDJJjP8PVAdiwKjN3AQ4OAHH0HwVVDyk+YvRmhYMr1Twj99p0Zevs44d77g3mcs/a8s2WLfXnBwOBR/7XamEGGhXIsI7YNINH84uGkeNqvxLoWOekOPAr6W1ZU9/ghyAywwxT4Fr9xqXvzO9fgS+TyRmD1RlPLI2T67rW7H/AT4Wz+Jla76X3uY0/X03NrJWyvw/e7yETpZBTz/ODuXzUSndieqKumlVGx54FKzHl+FGTQxxeoCa+Dz8dkh4bYDzGJshJdTirRUaUpxPzYnce3sMQuJJA4lCRhCdSyw2hFCZRjAKnAx/Lea/HZplf0d41QDzEGVkaO7BJg9TSCTjRcaB9ku3qvOO//NyYL7VH7s4wu9E/Phsfx2D563pgtis35ZhndWWXLTw79GRIZEJ9QWjiu7LtKRb8sOXH5M1QI/1Pv8GraTPTif3fo=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(376002)(396003)(39860400002)(346002)(136003)(451199021)(36840700001)(40470700004)(46966006)(40460700003)(2906002)(41300700001)(5660300002)(8676002)(8936002)(82310400005)(36756003)(55016003)(40480700001)(86362001)(7696005)(478600001)(336012)(47076005)(426003)(36860700001)(186003)(16526019)(6286002)(26005)(1076003)(2616005)(54906003)(110136005)(356005)(82740400003)(316002)(7636003)(4326008)(6636002)(70586007)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jun 2023 01:24:35.2321 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 92ca5bf4-83f9-4fd1-4d50-08db712d1b9e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF000252A3.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW4PR12MB6732", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Nvidia HW provides a synchronous mechanism between QPs. When\ncreating the QPs, user can set one as primary and another as\nfollower. The follower QP's WQE execution can be controlled\nby primary QP via SEND_EN WQE.\n\nThis commit introduces the SEND_EN WQE to improve the WQE\nexecution sync-up between primary and follower QPs.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++\n drivers/common/mlx5/mlx5_prm.h | 11 +++++++++++\n 3 files changed, 20 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 4332081165..ef87862a6d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2475,6 +2475,12 @@ mlx5_devx_cmd_create_qp(void *ctx,\n \t\t\t\t attr->dbr_umem_valid);\n \t\t\tMLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);\n \t\t}\n+\t\tif (attr->cd_master)\n+\t\t\tMLX5_SET(qpc, qpc, cd_master, attr->cd_master);\n+\t\tif (attr->cd_slave_send)\n+\t\t\tMLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);\n+\t\tif (attr->cd_slave_recv)\n+\t\t\tMLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);\n \t\tMLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);\n \t\tMLX5_SET64(create_qp_in, in, wq_umem_offset,\n \t\t\t attr->wq_umem_offset);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex cb3f3a211b..e071cd841f 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -559,6 +559,9 @@ struct mlx5_devx_qp_attr {\n \tuint64_t wq_umem_offset;\n \tuint32_t user_index:24;\n \tuint32_t mmo:1;\n+\tuint32_t cd_master:1;\n+\tuint32_t cd_slave_send:1;\n+\tuint32_t cd_slave_recv:1;\n };\n \n struct mlx5_devx_virtio_q_couners_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 6b48c6ca32..2d0a34ffbc 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -589,6 +589,17 @@ struct mlx5_rdma_write_wqe {\n \tstruct mlx5_wqe_dseg dseg[];\n } __rte_packed;\n \n+struct mlx5_wqe_send_en_seg {\n+\tuint32_t reserve[2];\n+\tuint32_t sqnpc;\n+\tuint32_t qpn;\n+} __rte_packed;\n+\n+struct mlx5_wqe_send_en_wqe {\n+\tstruct mlx5_wqe_cseg ctr;\n+\tstruct mlx5_wqe_send_en_seg sseg;\n+} __rte_packed;\n+\n #ifdef PEDANTIC\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n", "prefixes": [ "v3", "6/9" ] }