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GET /api/patches/127434/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 127434,
    "url": "http://patches.dpdk.org/api/patches/127434/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230525095904.3967080-27-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230525095904.3967080-27-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230525095904.3967080-27-ndabilpuram@marvell.com",
    "date": "2023-05-25T09:58:59",
    "name": "[v3,27/32] common/cnxk: configure PFC on SPB aura",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "3974eaffb00a8d8473ae31eb4c9f7f4f7fef9d89",
    "submitter": {
        "id": 1202,
        "url": "http://patches.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230525095904.3967080-27-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 28180,
            "url": "http://patches.dpdk.org/api/series/28180/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28180",
            "date": "2023-05-25T09:58:36",
            "name": "[v3,01/32] common/cnxk: allocate dynamic BPIDs",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/28180/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/127434/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/127434/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E3B0942B9A;\n\tThu, 25 May 2023 12:38:36 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6C83642D5C;\n\tThu, 25 May 2023 12:38:30 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id E951A42D3B\n for <dev@dpdk.org>; Thu, 25 May 2023 12:38:28 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 34PA2X1N020293 for <dev@dpdk.org>; Thu, 25 May 2023 03:38:28 -0700",
            "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qt5jng44u-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 25 May 2023 03:38:27 -0700",
            "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 25 May 2023 03:38:26 -0700",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 25 May 2023 03:38:26 -0700",
            "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 1F1895B6E9E;\n Thu, 25 May 2023 03:00:36 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=jkd+9g2j9Vo2n/Oh425aiK2uubTeIQC/7skbTG3/oMw=;\n b=VFrW3cCfgGB7D+k68QBEvHnWBxdCsgfZ2asawUAq0y61U6zGc2HteRrfRvDxFlc5g7lL\n oQehmJ23jyRx5OzG8LzAtbQWyPp6m6ua/BE9fFQ6M+O90XNZGLXNaVmkTxzI01aaEJKn\n Mftqp9pdI+G7Q4tPLvTzikbT9HbA0oJwVQB1rcOlD31iQVRmua35C1ygcWmC0cdUteRD\n +/6jW4oC7ViAySJ0wOqwE+3Wc2mqtFxcsUCr/XFCQU9xls65tFz+RrYqZiWH6/fyzbph\n 6hgSDQctSBELOR6ENblZAESog7Nfv7XfzchrEqOmTfRXj1NumpMOx0g6zpafpoPGVkVr 3g==",
        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>",
        "CC": "<jerinj@marvell.com>, <dev@dpdk.org>",
        "Subject": "[PATCH v3 27/32] common/cnxk: configure PFC on SPB aura",
        "Date": "Thu, 25 May 2023 15:28:59 +0530",
        "Message-ID": "<20230525095904.3967080-27-ndabilpuram@marvell.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230525095904.3967080-1-ndabilpuram@marvell.com>",
        "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>\n <20230525095904.3967080-1-ndabilpuram@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-ORIG-GUID": "Gjh_S92t39N-rx2Mjc_84VTALD4S0iWa",
        "X-Proofpoint-GUID": "Gjh_S92t39N-rx2Mjc_84VTALD4S0iWa",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-05-25_06,2023-05-24_01,2023-05-22_02",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nA RQ can be configured with lpb_aura and spb_aura at the same time\nand both can contribute to generate aura based back pressure from\nNIX to RPM.\n\nBut currently PFC configuration are applied on lpb_aura only and\nspb_aura does not contribute to create back pressure.\n\nPatch adds support for the same.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h    | 1 +\n drivers/common/cnxk/roc_nix_fc.c | 6 ++++++\n 2 files changed, 7 insertions(+)",
    "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 548854952b..f60e546c01 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -198,6 +198,7 @@ struct roc_nix_fc_cfg {\n \t\t\tuint16_t cq_drop;\n \t\t\tbool enable;\n \t\t\tuint64_t pool;\n+\t\t\tuint64_t spb_pool;\n \t\t\tuint64_t pool_drop_pct;\n \t\t} rq_cfg;\n \ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 21e3b7d5bd..44eade5ba6 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -303,6 +303,12 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\t\t\t      fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n \t\t\t\t      fc_cfg->rq_cfg.tc, pool_drop_pct);\n \n+\t\tif (rq->spb_ena) {\n+\t\t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.spb_pool,\n+\t\t\t\t\t      fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n+\t\t\t\t\t      fc_cfg->rq_cfg.tc, pool_drop_pct);\n+\t\t}\n+\n \t\tif (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle)\n \t\t\troc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle,\n \t\t\t\t\t      fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,\n",
    "prefixes": [
        "v3",
        "27/32"
    ]
}