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GET /api/patches/127373/?format=api
{ "id": 127373, "url": "http://patches.dpdk.org/api/patches/127373/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230525074041.2370704-4-dongzhou@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230525074041.2370704-4-dongzhou@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230525074041.2370704-4-dongzhou@nvidia.com", "date": "2023-05-25T07:40:41", "name": "[v3,3/3] net/mlx5/hws: add support for infiniband BTH match", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ec6b8aa7de389d6c44095f69ffdc409e88981b21", "submitter": { "id": 2011, "url": "http://patches.dpdk.org/api/people/2011/?format=api", "name": "Dong Zhou", "email": "dongzhou@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230525074041.2370704-4-dongzhou@nvidia.com/mbox/", "series": [ { "id": 28170, "url": "http://patches.dpdk.org/api/series/28170/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28170", "date": "2023-05-25T07:40:38", "name": "add support for infiniband BTH match", "version": 3, "mbox": "http://patches.dpdk.org/series/28170/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/127373/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/127373/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D2DFD42B95;\n\tThu, 25 May 2023 09:41:40 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 701E842D3A;\n\tThu, 25 May 2023 09:41:39 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2050.outbound.protection.outlook.com [40.107.223.50])\n by mails.dpdk.org (Postfix) with ESMTP id 3130542D31\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dong Zhou <dongzhou@nvidia.com>", "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v3 3/3] net/mlx5/hws: add support for infiniband BTH match", "Date": "Thu, 25 May 2023 10:40:41 +0300", "Message-ID": "<20230525074041.2370704-4-dongzhou@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230525074041.2370704-1-dongzhou@nvidia.com>", "References": "<20230524100805.2215154-1-dongzhou@nvidia.com>\n <20230525074041.2370704-1-dongzhou@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT076:EE_|BL3PR12MB6452:EE_", "X-MS-Office365-Filtering-Correlation-Id": "653295e1-5c8d-419f-ed88-08db5cf37710", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n oM0P3hLoIJQ7gWP4BWE9EzvD9+FtEJw0xWBUk76RNCW2GMpFyqt6b5wt9Ab5QHlRCxnVc3Zlilj7J/Zf5X93PBivL/qRZj9kf9KToH82BFkP8zOAE1dILU2SrnnSWrileS1EheSW3EDEGiTHUwV6+oNEfH2pJ3GL1Fx7oCR6UvUABqfpq+xrFxYKzd1lIEcx6Rj6ik8X+L/ughhmK5eJzufyl6zIk3zDcr3XTAlj2aPK2vkPxJJmu7Ye2CIBNpTqjKdyf0A+e7fwWxixjgTwaekgyDeknqJWSAgp1sw700GlSAsKvmdQ1XePQlNZjY3b1U3FAnye6Fwpm1Nl0W/FIw81SoonSCc5uhpEZnhXVzuI4PevuxJ9eQoTH6dzRx8N4oFhqJm7aPf+dbN25c+8LXhfxch08IkCMReO+lNGupPy+JuBp7Womfshhh/n39Jn/eYtgM9kkplbcSsUeemuanikHIQu51w0WnjdShi6tC3t8xCcNJtRge+yizhLwWZHh2cNXpQXmu5L+ooOjAqGL5UOYCR5ZpPaVT/JIEl1sJkQ4fKomo9Vph1b6jirnO6JSLLYqqDWWyt/1ZjZVVPtykDzg2gnkIVO497o/72wdpL1R4RJaoei3BIFWJwhJFg8od5aF8dyLMY49cjHJvz6ddK/dmSYVZZKAUt8W2UEDT93xq5M0yYTfDWwrpeTp9E/nQTaadVQg2ZC34VxjbgpUvqHHOt+uzWhY+hf3a4ggnec4NnPqsiIs+WLHljDB8F3", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199021)(40470700004)(46966006)(36840700001)(70586007)(6636002)(4326008)(36756003)(8676002)(8936002)(5660300002)(107886003)(70206006)(316002)(110136005)(54906003)(478600001)(41300700001)(7696005)(40460700003)(6666004)(40480700001)(55016003)(7636003)(356005)(82740400003)(36860700001)(2906002)(16526019)(6286002)(186003)(83380400001)(47076005)(426003)(336012)(1076003)(86362001)(2616005)(82310400005)(26005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 May 2023 07:41:34.5901 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 653295e1-5c8d-419f-ed88-08db5cf37710", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT076.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL3PR12MB6452", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support to match opcode and dst_qp fields in\ninfiniband BTH. Currently, only the RoCEv2 packet is supported,\nthe input BTH match item is defaulted to match one RoCEv2 packet.\n\nSigned-off-by: Dong Zhou <dongzhou@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 76 ++++++++++++++++++++++++++-\n drivers/net/mlx5/hws/mlx5dr_definer.h | 2 +\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 3 files changed, 78 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex f92d3e8e1f..1a427c9b64 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -10,6 +10,7 @@\n #define ETH_TYPE_IPV6_VXLAN\t0x86DD\n #define ETH_VXLAN_DEFAULT_PORT\t4789\n #define IP_UDP_PORT_MPLS\t6635\n+#define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n \n #define STE_NO_VLAN\t0x0\n@@ -171,7 +172,9 @@ struct mlx5dr_definer_conv_data {\n \tX(SET_BE16,\tgre_opt_checksum,\tv->checksum_rsvd.checksum,\trte_flow_item_gre_opt) \\\n \tX(SET,\t\tmeter_color,\t\trte_col_2_mlx5_col(v->color),\trte_flow_item_meter_color) \\\n \tX(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \\\n-\tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)\n+\tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \\\n+\tX(SET,\t\tib_l4_udp_port,\t\tUDP_ROCEV2_PORT,\trte_flow_item_ib_bth) \\\n+\tX(SET,\t\tib_l4_opcode,\t\tv->hdr.opcode,\t\trte_flow_item_ib_bth)\n \n /* Item set function format */\n #define X(set_type, func_name, value, item_type) \\\n@@ -583,6 +586,16 @@ mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl));\n }\n \n+static void\n+mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_ib_bth *v = item_spec;\n+\n+\tmemcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp));\n+}\n+\n static int\n mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -2041,6 +2054,63 @@ mlx5dr_definer_conv_item_flex_parser(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t struct rte_flow_item *item,\n+\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_ib_bth *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\t/* In order to match on RoCEv2(layer4 ib), we must match\n+\t * on ip_protocol and l4_dport.\n+\t */\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_udp_protocol_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ib_l4_udp_port_set;\n+\t\t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n+\t\t}\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver ||\n+\t\tm->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 ||\n+\t\tm->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (m->hdr.opcode) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_OPCODE];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ib_l4_opcode_set;\n+\t\tDR_CALC_SET_HDR(fc, ib_l4, opcode);\n+\t}\n+\n+\tif (!is_mem_zero(m->hdr.dst_qp, 3)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_QPN];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ib_l4_qp_set;\n+\t\tDR_CALC_SET_HDR(fc, ib_l4, qp);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_match_template *mt,\n@@ -2182,6 +2252,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\titem_flags |= MLX5_FLOW_LAYER_MPLS;\n \t\t\tcd.mpls_idx++;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\t\tret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_IB_BTH;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex 90ec4ce845..6b645f4cf0 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -134,6 +134,8 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS2_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS3_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,\n+\tMLX5DR_DEFINER_FNAME_IB_L4_OPCODE,\n+\tMLX5DR_DEFINER_FNAME_IB_L4_QPN,\n \tMLX5DR_DEFINER_FNAME_MAX,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 853c94af9c..f9e7f844ea 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4969,6 +4969,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:\n \t\tcase RTE_FLOW_ITEM_TYPE_ESP:\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "v3", "3/3" ] }