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GET /api/patches/127103/?format=api
{ "id": 127103, "url": "http://patches.dpdk.org/api/patches/127103/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230519083110.809913-2-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230519083110.809913-2-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230519083110.809913-2-wenjing.qiao@intel.com", "date": "2023-05-19T08:31:04", "name": "[v4,1/7] common/idpf: fix 64b timestamp roll over issue", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "2c4823545025eebba80a766d083632a988a6cd77", "submitter": { "id": 2680, "url": "http://patches.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230519083110.809913-2-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 28088, "url": "http://patches.dpdk.org/api/series/28088/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28088", "date": "2023-05-19T08:31:03", "name": "fix idpf and cpfl timestamp", "version": 4, "mbox": "http://patches.dpdk.org/series/28088/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/127103/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/127103/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8495942B47;\n\tFri, 19 May 2023 10:37:00 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 755604282D;\n\tFri, 19 May 2023 10:37:00 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 8E27940F16;\n Fri, 19 May 2023 10:36:58 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 May 2023 01:36:57 -0700", "from dpdk-wenjing-01.sh.intel.com ([10.67.118.161])\n by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:36:55 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1684485418; x=1716021418;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=ACqcnx8xDgGo6vtDtcl3UGmMonmAob34dU+jelCNfP4=;\n b=b7J8+8KGAgMT3KvYcm1UKF9S7f6MTrSIxYMNXwJks9jZxeeIzGfCfJEa\n RfZQtTEesZ/WVPfyjrOrFtkGoGofvhNIiyCLkLDCq2KdvuBW2cvYZ8Nab\n S47kcIIv5kaMvqkt7BWedMMD0gBOQFzwU6tCm/3np/4T6WsF/YbNB/4z+\n L2mpzUimaOTwi/YvGSq+YIN6t5Irg1L0nQebsb3ktxtRrQzIXOOxYBUMP\n tT4VlvFVdDdmA6vJQcZZt/b/4qoKVwD/38PIYEXKBtbzaSSKpYT0ohXWe\n mHihlOp6KpyrTAgByZ4WnzPyK2GKTw/sV6Ygb4JLO6/+5i4d/03Uo3Xce w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10714\"; a=\"354670369\"", "E=Sophos;i=\"6.00,176,1681196400\"; d=\"scan'208\";a=\"354670369\"", "E=McAfee;i=\"6600,9927,10714\"; a=\"772216212\"", "E=Sophos;i=\"6.00,176,1681196400\"; d=\"scan'208\";a=\"772216212\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com,\n Wenjing Qiao <wenjing.qiao@intel.com>,\n stable@dpdk.org", "Subject": "[PATCH v4 1/7] common/idpf: fix 64b timestamp roll over issue", "Date": "Fri, 19 May 2023 04:31:04 -0400", "Message-Id": "<20230519083110.809913-2-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230519083110.809913-1-wenjing.qiao@intel.com>", "References": "<20230424091707.488045-2-wenjing.qiao@intel.com>\n <20230519083110.809913-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Reading MTS register at first packet will cause timestamp\nroll over issue. To support calculating 64b timestamp, need\nan alarm to save main time from registers every 1 second.\n\nFixes: 8c6098afa075 (\"common/idpf: add Rx/Tx data path\")\nCc: stable@dpdk.org\n\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/common/idpf/idpf_common_rxtx.c | 126 ++++++++++++++-----------\n drivers/common/idpf/idpf_common_rxtx.h | 6 +-\n drivers/common/idpf/version.map | 2 +\n 3 files changed, 77 insertions(+), 57 deletions(-)", "diff": "diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c\nindex fc87e3e243..b487c2a8a6 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.c\n+++ b/drivers/common/idpf/idpf_common_rxtx.c\n@@ -4,6 +4,7 @@\n \n #include <rte_mbuf_dyn.h>\n #include <rte_errno.h>\n+#include <rte_alarm.h>\n \n #include \"idpf_common_rxtx.h\"\n \n@@ -349,6 +350,46 @@ idpf_qc_tx_queue_release(void *txq)\n \trte_free(q);\n }\n \n+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND\t10000\n+static void\n+idpf_dev_read_time_hw(void *cb_arg)\n+{\n+#ifdef RTE_ARCH_X86_64\n+\tstruct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;\n+\tuint32_t hi, lo, lo2;\n+\tint rc = 0;\n+\tstruct idpf_hw *hw = &ad->hw;\n+\n+\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n+\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,\n+\t\t PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n+\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n+\t/*\n+\t * On typical system, the delta between lo and lo2 is ~1000ns,\n+\t * so 10000 seems a large-enough but not overly-big guard band.\n+\t */\n+\tif (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))\n+\t\tlo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\telse\n+\t\tlo2 = lo;\n+\n+\tif (lo2 < lo) {\n+\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n+\t}\n+\n+\tad->time_hw = ((uint64_t)hi << 32) | lo;\n+#else /* !RTE_ARCH_X86_64 */\n+\tad->time_hw = 0;\n+#endif /* RTE_ARCH_X86_64 */\n+\n+\t/* re-alarm watchdog */\n+\trc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);\n+\tif (rc)\n+\t\tDRV_LOG(ERR, \"Failed to reset device watchdog alarm\");\n+}\n+\n int\n idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)\n {\n@@ -366,6 +407,24 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)\n \treturn 0;\n }\n \n+\n+int\n+idpf_rx_timestamp_start(struct idpf_adapter *base)\n+{\n+\trte_eal_alarm_set(1000 * 1000,\n+\t\t\t &idpf_dev_read_time_hw,\n+\t\t\t (void *)base);\n+\treturn 0;\n+}\n+\n+int\n+idpf_rx_timestamp_stop(struct idpf_adapter *base)\n+{\n+\trte_eal_alarm_cancel(idpf_dev_read_time_hw,\n+\t\t\t base);\n+\treturn 0;\n+}\n+\n int\n idpf_qc_single_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)\n {\n@@ -442,56 +501,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)\n \treturn 0;\n }\n \n-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000\n /* Helper function to convert a 32b nanoseconds timestamp to 64b. */\n static inline uint64_t\n-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,\n-\t\t\t uint32_t in_timestamp)\n+idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp)\n {\n-#ifdef RTE_ARCH_X86_64\n-\tstruct idpf_hw *hw = &ad->hw;\n \tconst uint64_t mask = 0xFFFFFFFF;\n-\tuint32_t hi, lo, lo2, delta;\n+\tconst uint32_t half_overflow_duration = 0x1 << 31;\n+\tuint32_t delta;\n \tuint64_t ns;\n \n-\tif (flag != 0) {\n-\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n-\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |\n-\t\t\t PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n-\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n-\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n-\t\t/*\n-\t\t * On typical system, the delta between lo and lo2 is ~1000ns,\n-\t\t * so 10000 seems a large-enough but not overly-big guard band.\n-\t\t */\n-\t\tif (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))\n-\t\t\tlo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n-\t\telse\n-\t\t\tlo2 = lo;\n-\n-\t\tif (lo2 < lo) {\n-\t\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n-\t\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n-\t\t}\n-\n-\t\tad->time_hw = ((uint64_t)hi << 32) | lo;\n-\t}\n-\n-\tdelta = (in_timestamp - (uint32_t)(ad->time_hw & mask));\n-\tif (delta > (mask / 2)) {\n-\t\tdelta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);\n-\t\tns = ad->time_hw - delta;\n+\tdelta = (in_timestamp - (uint32_t)(time_hw & mask));\n+\tif (delta > half_overflow_duration) {\n+\t\tdelta = ((uint32_t)(time_hw & mask) - in_timestamp);\n+\t\tns = time_hw - delta;\n \t} else {\n-\t\tns = ad->time_hw + delta;\n+\t\tns = time_hw + delta;\n \t}\n-\n \treturn ns;\n-#else /* !RTE_ARCH_X86_64 */\n-\tRTE_SET_USED(ad);\n-\tRTE_SET_USED(flag);\n-\tRTE_SET_USED(in_timestamp);\n-\treturn 0;\n-#endif /* RTE_ARCH_X86_64 */\n }\n \n #define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S\t\t\t\t\\\n@@ -659,9 +685,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \trx_desc_ring = rxq->rx_ring;\n \tptype_tbl = rxq->adapter->ptype_tbl;\n \n-\tif ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)\n-\t\trxq->hw_register_set = 1;\n-\n \twhile (nb_rx < nb_pkts) {\n \t\trx_desc = &rx_desc_ring[rx_id];\n \n@@ -720,10 +743,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tif (idpf_timestamp_dynflag > 0 &&\n \t\t (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {\n \t\t\t/* timestamp */\n-\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad,\n-\t\t\t\t\t\t\t rxq->hw_register_set,\n+\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,\n \t\t\t\t\t\t\t rte_le_to_cpu_32(rx_desc->ts_high));\n-\t\t\trxq->hw_register_set = 0;\n \t\t\t*RTE_MBUF_DYNFIELD(rxm,\n \t\t\t\t\t idpf_timestamp_dynfield_offset,\n \t\t\t\t\t rte_mbuf_timestamp_t *) = ts_ns;\n@@ -1077,9 +1098,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \trx_ring = rxq->rx_ring;\n \tptype_tbl = rxq->adapter->ptype_tbl;\n \n-\tif ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)\n-\t\trxq->hw_register_set = 1;\n-\n \twhile (nb_rx < nb_pkts) {\n \t\trxdp = &rx_ring[rx_id];\n \t\trx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);\n@@ -1142,10 +1160,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tif (idpf_timestamp_dynflag > 0 &&\n \t\t (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {\n \t\t\t/* timestamp */\n-\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad,\n-\t\t\t\t\t rxq->hw_register_set,\n+\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,\n \t\t\t\t\t rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));\n-\t\t\trxq->hw_register_set = 0;\n \t\t\t*RTE_MBUF_DYNFIELD(rxm,\n \t\t\t\t\t idpf_timestamp_dynfield_offset,\n \t\t\t\t\t rte_mbuf_timestamp_t *) = ts_ns;\n@@ -1272,10 +1288,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tif (idpf_timestamp_dynflag > 0 &&\n \t\t (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {\n \t\t\t/* timestamp */\n-\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad,\n-\t\t\t\trxq->hw_register_set,\n+\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,\n \t\t\t\trte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));\n-\t\t\trxq->hw_register_set = 0;\n \t\t\t*RTE_MBUF_DYNFIELD(rxm,\n \t\t\t\t\t idpf_timestamp_dynfield_offset,\n \t\t\t\t\t rte_mbuf_timestamp_t *) = ts_ns;\ndiff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h\nindex 6cb83fc0a6..53049b1a31 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.h\n+++ b/drivers/common/idpf/idpf_common_rxtx.h\n@@ -145,7 +145,6 @@ struct idpf_rx_queue {\n \tstruct idpf_rx_queue *bufq2;\n \n \tuint64_t offloads;\n-\tuint32_t hw_register_set;\n };\n \n struct idpf_tx_entry {\n@@ -303,4 +302,9 @@ __rte_internal\n uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts);\n \n+__rte_internal\n+int idpf_rx_timestamp_start(struct idpf_adapter *base);\n+\n+__rte_internal\n+int idpf_rx_timestamp_stop(struct idpf_adapter *base);\n #endif /* _IDPF_COMMON_RXTX_H_ */\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex 70334a1b03..661c7f5cb9 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -34,6 +34,8 @@ INTERNAL {\n \tidpf_qc_tx_thresh_check;\n \tidpf_qc_tx_vec_avx512_setup;\n \tidpf_qc_txq_mbufs_release;\n+\tidpf_rx_timestamp_start;\n+\tidpf_rx_timestamp_stop;\n \n \tidpf_vc_api_version_check;\n \tidpf_vc_caps_get;\n", "prefixes": [ "v4", "1/7" ] }