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GET /api/patches/127081/?format=api
{ "id": 127081, "url": "http://patches.dpdk.org/api/patches/127081/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230519051055.106893-10-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230519051055.106893-10-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230519051055.106893-10-beilei.xing@intel.com", "date": "2023-05-19T05:10:53", "name": "[v2,08/10] net/cpfl: enable write back based on ITR expire", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5f2c822a4b4fac4edf52175f58fc705d341f72e7", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230519051055.106893-10-beilei.xing@intel.com/mbox/", "series": [ { "id": 28078, "url": "http://patches.dpdk.org/api/series/28078/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=28078", "date": "2023-05-19T05:10:44", "name": "add hairpin queue support", "version": 2, "mbox": "http://patches.dpdk.org/series/28078/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/127081/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/127081/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AD1EE42B43;\n\tFri, 19 May 2023 07:36:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DAB4A42D65;\n\tFri, 19 May 2023 07:35:36 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 5DAB042D51\n for <dev@dpdk.org>; Fri, 19 May 2023 07:35:32 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 May 2023 22:35:14 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 22:35:13 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1684474532; x=1716010532;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=tyjyD9pM8d2lxb+EltU8AFoLyMw+AGV5au2lABQGISE=;\n b=CphKlGdhNO13qhx6gPmCG5cPF6P4XsxxntJDBFVRThqdAy/d5VZkcrWW\n qgG/vhkHUN4TCci+LDNiBtU9LpyGtpEJmiuwyLIW05keJbStCVc/fWtDU\n 02DE1PvKBRleCfUc3jcoG9vD1Xyd3RwKlfjJp3GEnh/l3T5DrFLePB4bk\n M8DcDkpUhqG68TCpymNtipazaZHK0mKJrB9VImiMfqhq5tk3w4bwjLL+7\n nQyHC8jN3TXOmgOaF9nP+VqslcEm/kDqp4kbVnoZ1T+LRprB2tkmpUdbU\n T/TqJaEnt3bLercSSGMHJRGQhyzMHGuqISxmWlcR5vFEV89UnnazojAjT A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10714\"; a=\"438639535\"", "E=Sophos;i=\"6.00,175,1681196400\"; d=\"scan'208\";a=\"438639535\"", "E=McAfee;i=\"6600,9927,10714\"; a=\"705462474\"", "E=Sophos;i=\"6.00,175,1681196400\"; d=\"scan'208\";a=\"705462474\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH v2 08/10] net/cpfl: enable write back based on ITR expire", "Date": "Fri, 19 May 2023 05:10:53 +0000", "Message-Id": "<20230519051055.106893-10-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20230519051055.106893-1-beilei.xing@intel.com>", "References": "<20230421065048.106899-1-beilei.xing@intel.com>\n <20230519051055.106893-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThis patch enabls write back based on ITR expire\n(WR_ON_ITR) for hairpin queue.\n\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/idpf_common_device.c | 75 ++++++++++++++++++++++++\n drivers/common/idpf/idpf_common_device.h | 4 ++\n drivers/common/idpf/version.map | 1 +\n drivers/net/cpfl/cpfl_ethdev.c | 13 +++-\n 4 files changed, 92 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/idpf/idpf_common_device.c b/drivers/common/idpf/idpf_common_device.c\nindex 3b58bdd41e..86a4a54f9b 100644\n--- a/drivers/common/idpf/idpf_common_device.c\n+++ b/drivers/common/idpf/idpf_common_device.c\n@@ -559,6 +559,81 @@ idpf_vport_irq_map_config(struct idpf_vport *vport, uint16_t nb_rx_queues)\n \treturn ret;\n }\n \n+int\n+idpf_vport_irq_map_config_by_qids(struct idpf_vport *vport, uint32_t *qids, uint16_t nb_rx_queues)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_queue_vector *qv_map;\n+\tstruct idpf_hw *hw = &adapter->hw;\n+\tuint32_t dynctl_val, itrn_val;\n+\tuint32_t dynctl_reg_start;\n+\tuint32_t itrn_reg_start;\n+\tuint16_t i;\n+\tint ret;\n+\n+\tqv_map = rte_zmalloc(\"qv_map\",\n+\t\t\t nb_rx_queues *\n+\t\t\t sizeof(struct virtchnl2_queue_vector), 0);\n+\tif (qv_map == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate %d queue-vector map\",\n+\t\t\tnb_rx_queues);\n+\t\tret = -ENOMEM;\n+\t\tgoto qv_map_alloc_err;\n+\t}\n+\n+\t/* Rx interrupt disabled, Map interrupt only for writeback */\n+\n+\t/* The capability flags adapter->caps.other_caps should be\n+\t * compared with bit VIRTCHNL2_CAP_WB_ON_ITR here. The if\n+\t * condition should be updated when the FW can return the\n+\t * correct flag bits.\n+\t */\n+\tdynctl_reg_start =\n+\t\tvport->recv_vectors->vchunks.vchunks->dynctl_reg_start;\n+\titrn_reg_start =\n+\t\tvport->recv_vectors->vchunks.vchunks->itrn_reg_start;\n+\tdynctl_val = IDPF_READ_REG(hw, dynctl_reg_start);\n+\tDRV_LOG(DEBUG, \"Value of dynctl_reg_start is 0x%x\", dynctl_val);\n+\titrn_val = IDPF_READ_REG(hw, itrn_reg_start);\n+\tDRV_LOG(DEBUG, \"Value of itrn_reg_start is 0x%x\", itrn_val);\n+\t/* Force write-backs by setting WB_ON_ITR bit in DYN_CTL\n+\t * register. WB_ON_ITR and INTENA are mutually exclusive\n+\t * bits. Setting WB_ON_ITR bits means TX and RX Descs\n+\t * are written back based on ITR expiration irrespective\n+\t * of INTENA setting.\n+\t */\n+\t/* TBD: need to tune INTERVAL value for better performance. */\n+\titrn_val = (itrn_val == 0) ? IDPF_DFLT_INTERVAL : itrn_val;\n+\tdynctl_val = VIRTCHNL2_ITR_IDX_0 <<\n+\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n+\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n+\t\t itrn_val << PF_GLINT_DYN_CTL_INTERVAL_S;\n+\tIDPF_WRITE_REG(hw, dynctl_reg_start, dynctl_val);\n+\n+\tfor (i = 0; i < nb_rx_queues; i++) {\n+\t\t/* map all queues to the same vector */\n+\t\tqv_map[i].queue_id = qids[i];\n+\t\tqv_map[i].vector_id =\n+\t\t\tvport->recv_vectors->vchunks.vchunks->start_vector_id;\n+\t}\n+\tvport->qv_map = qv_map;\n+\n+\tret = idpf_vc_irq_map_unmap_config(vport, nb_rx_queues, true);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"config interrupt mapping failed\");\n+\t\tgoto config_irq_map_err;\n+\t}\n+\n+\treturn 0;\n+\n+config_irq_map_err:\n+\trte_free(vport->qv_map);\n+\tvport->qv_map = NULL;\n+\n+qv_map_alloc_err:\n+\treturn ret;\n+}\n+\n int\n idpf_vport_irq_unmap_config(struct idpf_vport *vport, uint16_t nb_rx_queues)\n {\ndiff --git a/drivers/common/idpf/idpf_common_device.h b/drivers/common/idpf/idpf_common_device.h\nindex 7cf2355bc9..1aa9d9516f 100644\n--- a/drivers/common/idpf/idpf_common_device.h\n+++ b/drivers/common/idpf/idpf_common_device.h\n@@ -212,5 +212,9 @@ int idpf_vport_info_init(struct idpf_vport *vport,\n \t\t\t struct virtchnl2_create_vport *vport_info);\n __rte_internal\n void idpf_vport_stats_update(struct virtchnl2_vport_stats *oes, struct virtchnl2_vport_stats *nes);\n+__rte_internal\n+int idpf_vport_irq_map_config_by_qids(struct idpf_vport *vport,\n+\t\t\t\t uint32_t *qids,\n+\t\t\t\t uint16_t nb_rx_queues);\n \n #endif /* _IDPF_COMMON_DEVICE_H_ */\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex 0e87dba2ae..e3a7ef0daa 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -74,6 +74,7 @@ INTERNAL {\n \tidpf_vport_info_init;\n \tidpf_vport_init;\n \tidpf_vport_irq_map_config;\n+\tidpf_vport_irq_map_config_by_qids;\n \tidpf_vport_irq_unmap_config;\n \tidpf_vport_rss_config;\n \tidpf_vport_stats_update;\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex fe34b38c45..2936d23be7 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -730,11 +730,22 @@ cpfl_dev_configure(struct rte_eth_dev *dev)\n static int\n cpfl_config_rx_queues_irqs(struct rte_eth_dev *dev)\n {\n+\tuint32_t qids[CPFL_MAX_P2P_NB_QUEUES + IDPF_DEFAULT_RXQ_NUM] = {0};\n \tstruct cpfl_vport *cpfl_vport = dev->data->dev_private;\n \tstruct idpf_vport *vport = &cpfl_vport->base;\n \tuint16_t nb_rx_queues = dev->data->nb_rx_queues;\n+\tstruct cpfl_rx_queue *cpfl_rxq;\n+\tint i;\n \n-\treturn idpf_vport_irq_map_config(vport, nb_rx_queues);\n+\tfor (i = 0; i < nb_rx_queues; i++) {\n+\t\tcpfl_rxq = dev->data->rx_queues[i];\n+\t\tif (cpfl_rxq->hairpin_info.hairpin_q)\n+\t\t\tqids[i] = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.rx_start_qid,\n+\t\t\t\t\t\t (i - cpfl_vport->nb_data_rxq));\n+\t\telse\n+\t\t\tqids[i] = cpfl_hw_qid_get(vport->chunks_info.rx_start_qid, i);\n+\t}\n+\treturn idpf_vport_irq_map_config_by_qids(vport, qids, nb_rx_queues);\n }\n \n /* Update hairpin_info for dev's tx hairpin queue */\n", "prefixes": [ "v2", "08/10" ] }