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GET /api/patches/126860/?format=api
{ "id": 126860, "url": "http://patches.dpdk.org/api/patches/126860/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230516054053.1396711-3-rongweil@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230516054053.1396711-3-rongweil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230516054053.1396711-3-rongweil@nvidia.com", "date": "2023-05-16T05:40:53", "name": "[v1,2/2] net/mlx5: fix VXLAN matching with zero value", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fded6ed065531f415bbdc0e2f6cd72b7d44ee991", "submitter": { "id": 2223, "url": "http://patches.dpdk.org/api/people/2223/?format=api", "name": "rongwei liu", "email": "rongweil@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230516054053.1396711-3-rongweil@nvidia.com/mbox/", "series": [ { "id": 27998, "url": "http://patches.dpdk.org/api/series/27998/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27998", "date": "2023-05-16T05:40:51", "name": "Fix VXLAN matching", "version": 1, "mbox": "http://patches.dpdk.org/series/27998/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126860/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126860/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 552D142B1C;\n\tTue, 16 May 2023 07:41:34 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A912B42D38;\n\tTue, 16 May 2023 07:41:30 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2068.outbound.protection.outlook.com [40.107.244.68])\n by mails.dpdk.org (Postfix) with ESMTP id BB67440A7A;\n Tue, 16 May 2023 07:41:29 +0200 (CEST)", "from MW2PR2101CA0016.namprd21.prod.outlook.com (2603:10b6:302:1::29)\n by IA1PR12MB6211.namprd12.prod.outlook.com (2603:10b6:208:3e5::5)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.30; 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helo=mail.nvidia.com; pr=C", "From": "Rongwei Liu <rongweil@nvidia.com>", "To": "<dev@dpdk.org>, <matan@nvidia.com>, <viacheslavo@nvidia.com>,\n <orika@nvidia.com>, <thomas@monjalon.net>", "CC": "<suanmingm@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH v1 2/2] net/mlx5: fix VXLAN matching with zero value", "Date": "Tue, 16 May 2023 08:40:53 +0300", "Message-ID": "<20230516054053.1396711-3-rongweil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230516054053.1396711-1-rongweil@nvidia.com>", "References": "<20230516054053.1396711-1-rongweil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT088:EE_|IA1PR12MB6211:EE_", "X-MS-Office365-Filtering-Correlation-Id": "04492973-db0b-4ea4-a980-08db55d03189", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n EoIvAyl/fRW8CeZh9UXjEH8/R36p/lJlIfvlrYsnvfbH6O/g64OHM01oe0YONchyYXVCtt1pdIQYqP8vthZqoqYlLKZPZfZsNulqtEd7EsajFNMMLE3JngA0AIoqAJ62DPQY2QIum8QwQYTKoegEhBm2K9WNPFPETjn35ONg4HoJ4UCIrhozUL2u514jUzmITh9LL1CWlfAxI7q968W9Lfly8kU+ITGm0Epekm+wvaGWbIGAf2vIIP8EBhKF9QqJctwmnQF1ROgQbwV6Lhu8MZoaB/zLQYv7xf1DT7ertBYkhSPxFnO0kJ78v6dOcvDYK5/813ccBTsC1Y4ydGbU0afLtBvzWz2XCLh+80ScJT4ebmEKETadt3W81CI3CA0YTUcPk/ukZLIdYzChcdZ55jTa1oJ9fRQdMVy1mkIdNTPTXLjhYGRdbLpn9L6bhwqB8Uzu5U58jSpkA0da+acaZEqDNeClEWweTRNO3HDAlClGhEHDbbwP5ECq1PPWXsgXO2RwWGmlm1eAfcEWTEvkFt5FWNo+/xgwN4TAYDttE6wnaRUxy5PD0keRASXFFsJAQFTpR0Ghg+2YamEL8NBgdbXuMoUrsJb5AzvNdCDXAMygfhij67JzPJ6HVMymcek/HEboaaLYVe+wBhYRjSAY5pnJ+lKo4t4R6eqiYEbjFJfnome4PAquhIaLqAmtPyo2KMlV2Gu4weIe1OInntHDK7sqa0cY+1su9gPdSvLLdxDlXZsnvuKnQnafd57Kjvm7", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(376002)(39860400002)(396003)(136003)(346002)(451199021)(36840700001)(40470700004)(46966006)(55016003)(86362001)(40460700003)(2906002)(82310400005)(40480700001)(316002)(70206006)(70586007)(4326008)(7696005)(6666004)(36756003)(47076005)(54906003)(478600001)(110136005)(36860700001)(336012)(83380400001)(26005)(8936002)(1076003)(82740400003)(16526019)(186003)(8676002)(356005)(7636003)(6286002)(426003)(41300700001)(2616005)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 May 2023 05:41:27.4627 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 04492973-db0b-4ea4-a980-08db55d03189", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT088.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6211", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "When an application wants to match VxLAN last_rsvd value zero,\nPMD sets the matching mask field to zero by mistake and it causes\ntraffic with any last_rsvd value hits. The matching mask should be\ntaken from application input directly, no need to perform the bit reset\noperation.\n\nFixes: cd4ab742064a (\"net/mlx5: split flow item matcher and value translation\")\nCc: suanmingm@nvidia.com\nCc: stable@dpdk.org\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 19 ++-----------------\n 1 file changed, 2 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex f44d621600..1abc4acad7 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9480,12 +9480,10 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,\n {\n \tconst struct rte_flow_item_vxlan *vxlan_m;\n \tconst struct rte_flow_item_vxlan *vxlan_v;\n-\tconst struct rte_flow_item_vxlan *vxlan_vv = item->spec;\n \tvoid *headers_v;\n \tvoid *misc_v;\n \tvoid *misc5_v;\n \tuint32_t tunnel_v;\n-\tuint32_t *tunnel_header_v;\n \tchar *vni_v;\n \tuint16_t dport;\n \tint size;\n@@ -9537,24 +9535,11 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,\n \t\t\tvni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];\n \t\treturn;\n \t}\n-\ttunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,\n-\t\t\t\t\t\t misc5_v,\n-\t\t\t\t\t\t tunnel_header_1);\n \ttunnel_v = (vxlan_v->hdr.vni[0] & vxlan_m->hdr.vni[0]) |\n \t\t (vxlan_v->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 8 |\n \t\t (vxlan_v->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 16;\n-\t*tunnel_header_v = tunnel_v;\n-\tif (key_type == MLX5_SET_MATCHER_SW_M) {\n-\t\ttunnel_v = (vxlan_vv->hdr.vni[0] & vxlan_m->hdr.vni[0]) |\n-\t\t\t (vxlan_vv->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 8 |\n-\t\t\t (vxlan_vv->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 16;\n-\t\tif (!tunnel_v)\n-\t\t\t*tunnel_header_v = 0x0;\n-\t\tif (vxlan_vv->hdr.rsvd1 & vxlan_m->hdr.rsvd1)\n-\t\t\t*tunnel_header_v |= vxlan_v->hdr.rsvd1 << 24;\n-\t} else {\n-\t\t*tunnel_header_v |= (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1) << 24;\n-\t}\n+\ttunnel_v |= (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1) << 24;\n+\tMLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, RTE_BE32(tunnel_v));\n }\n \n /**\n", "prefixes": [ "v1", "2/2" ] }