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GET /api/patches/126749/?format=api
{ "id": 126749, "url": "http://patches.dpdk.org/api/patches/126749/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230507073952.4061-6-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230507073952.4061-6-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230507073952.4061-6-getelson@nvidia.com", "date": "2023-05-07T07:39:52", "name": "[v3,5/5] mlx5dr: Definer, translate RTE quota item", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c9f092ee07893f5fc0f3df1e71a941994d4573e8", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230507073952.4061-6-getelson@nvidia.com/mbox/", "series": [ { "id": 27947, "url": "http://patches.dpdk.org/api/series/27947/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27947", "date": "2023-05-07T07:39:47", "name": "net/mlx5: support indirect quota flow action", "version": 3, "mbox": "http://patches.dpdk.org/series/27947/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126749/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126749/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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"Subject": "[PATCH v3 5/5] mlx5dr: Definer, translate RTE quota item", "Date": "Sun, 7 May 2023 10:39:52 +0300", "Message-ID": "<20230507073952.4061-6-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230507073952.4061-1-getelson@nvidia.com>", "References": "<20230118125556.23622-1-getelson@nvidia.com>\n <20230507073952.4061-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT113:EE_|BY5PR12MB4130:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cb28fe00-3bdc-484a-2e10-08db4ece5cb0", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n cpSXC5kBR7hDWnhjSnUvR6N7P0LZAgT5dgO+kiSwI5GsW7XNDh/YfaSfxUjj8ZnQWcJu1KZklJ2G/aK16muY+nuZ1eT7nn63E4OrLEjMGfC404Fl02Idxoea00vWkI6OfoYhGG/DB0/cQudjRviUmvGy9px/ccfxJtfTSWL/b919I97+z8sM0F/m4bwNzC54NtwEbSTPoh1DKfzYUzgKv0rdpMWmiUVoA1KLn4cIslYQfdbbdmfBkDespDXUfpYYFChSZdcwT5/NknhNwM9H05l37CjPpiK2xQaJEA1GdDbGabnkFsO42wvBAtBQRVsxfvhd9b4Q4qvWo/olgFpbz9D30/2hE66mffQ9CRoe3BMUuKmAeQoxTMry/rmvLO1GGx/T4W2jisHvCtq9ol+rXiE4rMnJ1/jcART0eR6tfUv+rSZpVQTRsrT5BVTjd/9HaM7XwlTXyr0pVFiYUT3eBUVp4aMUbpq4ZrccfNOaaSWgeZ7Y0mnw+VlEH3BtdackKdh5ghSHyXLqY1IiNVr2csJCkD48aOMya1zxLVpm7pcXLCLCeTHzD74dJgCX6qAVrnF6L1E8itgbNp+3mVD5ynlSBo1AKzIvAT42IFD6O2EQsL10B/I09VK3AoFGPRP7yBXPmRF2vsEGUCnrDJ0OPwo9W3EcgNajYIZF0Jmj/EpCu19puRa9+1YxASHHsdav", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(136003)(376002)(39850400004)(346002)(451199021)(46966006)(36840700001)(7696005)(478600001)(70206006)(6916009)(4326008)(70586007)(6666004)(316002)(54906003)(36756003)(86362001)(47076005)(336012)(426003)(83380400001)(1076003)(26005)(107886003)(2616005)(36860700001)(8676002)(8936002)(15650500001)(2906002)(5660300002)(82310400005)(41300700001)(55016003)(40480700001)(186003)(6286002)(16526019)(7636003)(82740400003)(356005)(32563001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2023 07:40:42.6461 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cb28fe00-3bdc-484a-2e10-08db4ece5cb0", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT113.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4130", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "MLX5 PMD implements QUOTA with Meter object.\nPMD Quota action translation implicitly increments\nMeter register value after HW assigns it.\nMeter register values are:\n HW QUOTA(HW+1) QUOTA state\nRED 0 1 (01b) BLOCK\nYELLOW 1 2 (10b) PASS\nGREEN 2 3 (11b) PASS\n\nQuota item checks Meter register bit 1 value to determine state:\n SPEC MASK\nPASS 2 (10b) 2 (10b)\nBLOCK 0 (00b) 2 (10b)\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 63 +++++++++++++++++++++++++++\n 1 file changed, 63 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex f92d3e8e1f..2d505f1908 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -21,6 +21,9 @@\n #define STE_UDP\t\t0x2\n #define STE_ICMP\t0x3\n \n+#define MLX5DR_DEFINER_QUOTA_BLOCK 0\n+#define MLX5DR_DEFINER_QUOTA_PASS 2\n+\n /* Setter function based on bit offset and mask, for 32bit DW*/\n #define _DR_SET_32(p, v, byte_off, bit_off, mask) \\\n \tdo { \\\n@@ -1447,6 +1450,62 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static void\n+mlx5dr_definer_quota_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_data, uint8_t *tag)\n+{\n+\t/**\n+\t * MLX5 PMD implements QUOTA with Meter object.\n+\t * PMD Quota action translation implicitly increments\n+\t * Meter register value after HW assigns it.\n+\t * Meter register values are:\n+\t * HW QUOTA(HW+1) QUOTA state\n+\t * RED 0 1 (01b) BLOCK\n+\t * YELLOW 1 2 (10b) PASS\n+\t * GREEN 2 3 (11b) PASS\n+\t *\n+\t * Quota item checks Meter register bit 1 value to determine state:\n+\t * SPEC MASK\n+\t * PASS 2 (10b) 2 (10b)\n+\t * BLOCK 0 (00b) 2 (10b)\n+\t *\n+\t * item_data is NULL when template quota item is non-masked:\n+\t * .. / quota / ..\n+\t */\n+\n+\tconst struct rte_flow_item_quota *quota = item_data;\n+\tuint32_t val;\n+\n+\tif (quota && quota->state == RTE_FLOW_QUOTA_STATE_BLOCK)\n+\t\tval = MLX5DR_DEFINER_QUOTA_BLOCK;\n+\telse\n+\t\tval = MLX5DR_DEFINER_QUOTA_PASS;\n+\n+\tDR_SET(tag, val, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n+static int\n+mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t __rte_unused struct rte_flow_item *item,\n+\t\t\t int item_idx)\n+{\n+\tint mtr_reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\tstruct mlx5dr_definer_fc *fc;\n+\n+\tif (mtr_reg < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tfc = mlx5dr_definer_get_register_fc(cd, mtr_reg);\n+\tif (!fc)\n+\t\treturn rte_errno;\n+\n+\tfc->tag_set = &mlx5dr_definer_quota_set;\n+\tfc->item_idx = item_idx;\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd,\n \t\t\t\t struct rte_flow_item *item,\n@@ -2163,6 +2222,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_METER_COLOR;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_QUOTA:\n+\t\t\tret = mlx5dr_definer_conv_item_quota(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_QUOTA;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:\n \t\t\tret = mlx5dr_definer_conv_item_ipv6_routing_ext(&cd, items, i);\n \t\t\titem_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :\n", "prefixes": [ "v3", "5/5" ] }