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GET /api/patches/126535/?format=api
{ "id": 126535, "url": "http://patches.dpdk.org/api/patches/126535/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230426102259.205992-4-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230426102259.205992-4-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230426102259.205992-4-wenjing.qiao@intel.com", "date": "2023-04-26T10:22:47", "name": "[v3,03/15] common/idpf/base: fix ITR register definitions for AVF", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b8924ee6beba0f99e5cf2e778fc91f257912fc6d", "submitter": { "id": 2680, "url": "http://patches.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230426102259.205992-4-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 27874, "url": "http://patches.dpdk.org/api/series/27874/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27874", "date": "2023-04-26T10:22:44", "name": "update idpf base code", "version": 3, "mbox": "http://patches.dpdk.org/series/27874/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126535/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126535/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D34EB42A02;\n\tWed, 26 Apr 2023 12:28:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E513E42D33;\n\tWed, 26 Apr 2023 12:28:02 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 65DF542D1D;\n Wed, 26 Apr 2023 12:28:00 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 03:27:57 -0700", "from dpdk-wenjing-01.sh.intel.com ([10.67.118.239])\n by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:55 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682504880; x=1714040880;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=FLOzSIp7OeQRV7sspPldHGbBKpUSnbSBjVpl2JmpW0Y=;\n b=QoKUbHGAe+WXsuczbipSOJkwkRIOcmIhAD8UZtzkYmjlbtNmVHMwsdhp\n f+AHHcQEwOky08/uwpNP19pVpycb06VTgg7gDPX/DRAidkINIJcvnEsVs\n XFj/9CoSX/V+lbiFjEZh5osERV1MCIYXugS3bBoz/THoXeMDLMUaMhFEV\n 3/ovI5AjdVrkyubRdm1fY2g7xxXe9KfFeCQyFv70Bfw0EHNovUijN9VtU\n FjvBhmb6Il6FivhkS+hM/c/jpTKBKq8aiibA8Ymigc0ADRAULFzbpmj5l\n pCR4oZ8NNmAy5D44VoUUWutPlX557z2sr6HIVebVX2jk79t7sA3WwhKfQ A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10691\"; a=\"327391501\"", "E=Sophos;i=\"5.99,227,1677571200\"; d=\"scan'208\";a=\"327391501\"", "E=McAfee;i=\"6600,9927,10691\"; a=\"1023552640\"", "E=Sophos;i=\"5.99,227,1677571200\"; d=\"scan'208\";a=\"1023552640\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com,\n Wenjing Qiao <wenjing.qiao@intel.com>,\n stable@dpdk.org, Priyalee Kushwaha <priyalee.kushwaha@intel.com>", "Subject": "[PATCH v3 03/15] common/idpf/base: fix ITR register definitions for\n AVF", "Date": "Wed, 26 Apr 2023 06:22:47 -0400", "Message-Id": "<20230426102259.205992-4-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230426102259.205992-1-wenjing.qiao@intel.com>", "References": "<20230421084043.135503-2-wenjing.qiao@intel.com>\n <20230426102259.205992-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Fix ITR register definitions for AVF1.0 and AVF2.0\n\nFixes: fb4ac04e9bfa (\"common/idpf: introduce common library\")\nCc: stable@dpdk.org\n\nSigned-off-by: Priyalee Kushwaha <priyalee.kushwaha@intel.com>\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/common/idpf/base/idpf_lan_pf_regs.h | 9 +++++++--\n drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 ++++++++++++-----\n 2 files changed, 19 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h\nindex 3df2347bd7..7f731ec3d6 100644\n--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h\n@@ -77,8 +77,13 @@\n #define PF_GLINT_DYN_CTL_WB_ON_ITR_M\tBIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)\n #define PF_GLINT_DYN_CTL_INTENA_MSK_S\t31\n #define PF_GLINT_DYN_CTL_INTENA_MSK_M\tBIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)\n-#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start))\n-#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) * 0x1000))\n+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is\n+ * spacing b/w itrn registers of the same vector.\n+ */\n+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n+\t\t((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n+/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */\n+#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n #define PF_GLINT_ITR_MAX_INDEX\t\t2\n #define PF_GLINT_ITR_INTERVAL_S\t\t0\n #define PF_GLINT_ITR_INTERVAL_M\t\tMAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S)\ndiff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h\nindex 9cd4f757d9..13c5c5a7da 100644\n--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h\n@@ -90,11 +90,18 @@\n #define VF_INT_DYN_CTLN_WB_ON_ITR_M\tBIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)\n #define VF_INT_DYN_CTLN_INTENA_MSK_S\t31\n #define VF_INT_DYN_CTLN_INTENA_MSK_M\tBIT(VF_INT_DYN_CTLN_INTENA_MSK_S)\n-#define VF_INT_ITR0(_i)\t\t\t(0x00004C00 + ((_i) * 4))\n-#define VF_INT_ITRN_V2(_i, _reg_start)\t((_reg_start) + (((_i)) * 4))\n-#define VF_INT_ITRN(_i, _INT)\t\t(0x00002800 + ((_i) * 4) + ((_INT) * 0x40))\n-#define VF_INT_ITRN_64(_i, _INT)\t(0x00002C00 + ((_i) * 4) + ((_INT) * 0x100))\n-#define VF_INT_ITRN_2K(_i, _INT)\t(0x00072000 + ((_i) * 4) + ((_INT) * 0x100))\n+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing\n+ * b/w itrn registers of the same vector\n+ */\n+#define VF_INT_ITR0(_ITR)\t\t(0x00004C00 + ((_ITR) * 4))\n+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n+\t\t ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n+/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */\n+#define VF_INT_ITRN(_INT, _ITR)\t(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))\n+/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */\n+#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))\n+/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */\n+#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n #define VF_INT_ITRN_MAX_INDEX\t\t2\n #define VF_INT_ITRN_INTERVAL_S\t\t0\n #define VF_INT_ITRN_INTERVAL_M\t\tMAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)\n", "prefixes": [ "v3", "03/15" ] }