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GET /api/patches/126460/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 126460,
    "url": "http://patches.dpdk.org/api/patches/126460/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230424122835.39493-2-sedara@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230424122835.39493-2-sedara@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230424122835.39493-2-sedara@marvell.com",
    "date": "2023-04-24T12:28:24",
    "name": "[v3,01/11] net/octeon_ep: support cnf95n and cnf95o SoC",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": true,
    "hash": "7176f9735075c645e32c18e10df50f41f69e92c3",
    "submitter": {
        "id": 2729,
        "url": "http://patches.dpdk.org/api/people/2729/?format=api",
        "name": "Sathesh B Edara",
        "email": "sedara@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230424122835.39493-2-sedara@marvell.com/mbox/",
    "series": [
        {
            "id": 27844,
            "url": "http://patches.dpdk.org/api/series/27844/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27844",
            "date": "2023-04-24T12:28:24",
            "name": "extend octeon ep driver functionality",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/27844/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/126460/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/126460/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6C419429DB;\n\tMon, 24 Apr 2023 14:28:51 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 03095410D0;\n\tMon, 24 Apr 2023 14:28:51 +0200 (CEST)",
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            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33OABOCh007100 for <dev@dpdk.org>; Mon, 24 Apr 2023 05:28:49 -0700",
            "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3q4f3p621s-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 24 Apr 2023 05:28:49 -0700",
            "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 24 Apr 2023 05:28:46 -0700",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 24 Apr 2023 05:28:46 -0700",
            "from localhost.marvell.com (unknown [10.106.27.249])\n by maili.marvell.com (Postfix) with ESMTP id B23933F70A0;\n Mon, 24 Apr 2023 05:28:46 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type : content-transfer-encoding; s=pfpt0220;\n bh=ZAseRYILUaqc21iU1XB7J8iA5OHXmqqs+BEL3XvilcE=;\n b=Ok/iKIUeNLP0cayxCfxeRsYLoMpj+XX8SD6Xd6bHghFnDegWEzBzX/62/0uYlyrZJxFp\n XUHtavobBxvO2EfNk7kFYJbN5VC05/mTZT6iDrJq4D1Tk+zhV9t7Z7xsFc3rdhKG792K\n jsEKn+UF7sw81sTYXVxCmjKg4tRapVVecMVx73rU93qPvggCB4ED75YDTNbfgYmxVtkI\n l9osBOcdJ1/ZELgndWWIjtSdaMdAaWdAJUvCjZgd7Xzs1Rwzp2Ns9sjmj+wQqN3ZexEe\n eO74B/PpzCel8TH0HVTlnPJXHwJDim/oPiEtfEaBqO+HsADEgK8PHkACQkyTxO+yulYo yA==",
        "From": "Sathesh Edara <sedara@marvell.com>",
        "To": "<sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>, \"Radha\n Mohan Chintakuntla\" <radhac@marvell.com>, Veerasenareddy Burru\n <vburru@marvell.com>",
        "CC": "<dev@dpdk.org>",
        "Subject": "[PATCH v3 01/11] net/octeon_ep: support cnf95n and cnf95o SoC",
        "Date": "Mon, 24 Apr 2023 05:28:24 -0700",
        "Message-ID": "<20230424122835.39493-2-sedara@marvell.com>",
        "X-Mailer": "git-send-email 2.31.1",
        "In-Reply-To": "<20230424122835.39493-1-sedara@marvell.com>",
        "References": "<20230405142537.1899973-2-sedara@marvell.com>\n <20230424122835.39493-1-sedara@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"UTF-8\"",
        "Content-Transfer-Encoding": "8bit",
        "X-Proofpoint-ORIG-GUID": "PbWFYs6oX0Nz-HTgvBlr-TT35I4cjpNE",
        "X-Proofpoint-GUID": "PbWFYs6oX0Nz-HTgvBlr-TT35I4cjpNE",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-24_07,2023-04-21_01,2023-02-09_01",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Adds the required functionality in the Octeon endpoint\ndriver to support the cnf95n and cnf95o endpoint device.\n\nSigned-off-by: Sathesh Edara <sedara@marvell.com>\n---\n drivers/net/octeon_ep/otx2_ep_vf.h    |  2 ++\n drivers/net/octeon_ep/otx_ep_ethdev.c | 13 +++++++++++--\n 2 files changed, 13 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/octeon_ep/otx2_ep_vf.h b/drivers/net/octeon_ep/otx2_ep_vf.h\nindex 757eeae9f0..8f00acd737 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.h\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.h\n@@ -115,6 +115,8 @@\n \n #define PCI_DEVID_CN9K_EP_NET_VF\t\t0xB203 /* OCTEON 9 EP mode */\n #define PCI_DEVID_CN98XX_EP_NET_VF\t\t0xB103\n+#define PCI_DEVID_CNF95N_EP_NET_VF\t\t0xB403\n+#define PCI_DEVID_CNF95O_EP_NET_VF\t\t0xB603\n \n int\n otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);\ndiff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c\nindex f43db1e398..24f62c3e49 100644\n--- a/drivers/net/octeon_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c\n@@ -105,6 +105,8 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n \t\tbreak;\n \tcase PCI_DEVID_CN9K_EP_NET_VF:\n \tcase PCI_DEVID_CN98XX_EP_NET_VF:\n+\tcase PCI_DEVID_CNF95N_EP_NET_VF:\n+\tcase PCI_DEVID_CNF95O_EP_NET_VF:\n \t\totx_epvf->chip_id = dev_id;\n \t\tret = otx2_ep_vf_setup_device(otx_epvf);\n \t\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n@@ -144,7 +146,9 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \tif (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;\n \telse if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF)\n+\t\t otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n \telse if (otx_epvf->chip_id == PCI_DEVID_CNXK_EP_NET_VF)\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n@@ -494,7 +498,10 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \totx_epvf->pdev = pdev;\n \n \totx_epdev_init(otx_epvf);\n-\tif (pdev->id.device_id == PCI_DEVID_CN9K_EP_NET_VF)\n+\tif (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n+\t    otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||\n+\t    otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||\n+\t    otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)\n \t\totx_epvf->pkind = SDP_OTX2_PKIND_FS0;\n \telse\n \t\totx_epvf->pkind = SDP_PKIND;\n@@ -524,6 +531,8 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = {\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_EP_NET_VF) },\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95N_EP_NET_VF) },\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95O_EP_NET_VF) },\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_EP_NET_VF) },\n \t{ .vendor_id = 0, /* sentinel */ }\n };\n",
    "prefixes": [
        "v3",
        "01/11"
    ]
}