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GET /api/patches/126367/?format=api
http://patches.dpdk.org/api/patches/126367/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230421084043.135503-4-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230421084043.135503-4-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230421084043.135503-4-wenjing.qiao@intel.com", "date": "2023-04-21T08:40:31", "name": "[v2,03/15] common/idpf: fix ITR register definitions for AVF", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b8924ee6beba0f99e5cf2e778fc91f257912fc6d", "submitter": { "id": 2680, "url": "http://patches.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230421084043.135503-4-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 27813, "url": "http://patches.dpdk.org/api/series/27813/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27813", "date": "2023-04-21T08:40:28", "name": "update idpf shared code", "version": 2, "mbox": "http://patches.dpdk.org/series/27813/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126367/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A2168429AA;\n\tFri, 21 Apr 2023 10:46:21 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DEB3E42D10;\n\tFri, 21 Apr 2023 10:46:09 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id DFDAF42BD9;\n Fri, 21 Apr 2023 10:46:05 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2023 01:46:04 -0700", "from dpdk-wenjing-01.sh.intel.com ([10.67.118.239])\n by fmsmga004.fm.intel.com with ESMTP; 21 Apr 2023 01:46:02 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682066766; x=1713602766;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=FLOzSIp7OeQRV7sspPldHGbBKpUSnbSBjVpl2JmpW0Y=;\n b=cL2BMW54OEYxioytMbGv64HjlloQHN3ahiF+z1zCumidsjwxLUl+2uwI\n /GPS8QgXIqec2zwkYXwKA7L34hGQ3T+EPEyH6VRtBh4/jnuldEk6vmWre\n mENJqovTTB1xGhUYJwi1duH3dKzrUqpgsKVi2HuTaOIiIfG2bQjpcL7Iy\n Q5xzyh3myvEjCKSaQF/kBuQxn4Y9esH0NPFzfjaSpZHCL0oa69vWMqg9/\n OLxHayoVFZinw8kShnLyNOvoWVz73lQ0YVA6NWXEaIlozmK1VL7Y8xlL5\n cxNRXOp+oN1e5nmRKErJHeY2gDgCKKVgpQ4RcBb2on+2+bV1wvm49+kpX A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10686\"; a=\"334822833\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"334822833\"", "E=McAfee;i=\"6600,9927,10686\"; a=\"761501395\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"761501395\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, Wenjing Qiao <wenjing.qiao@intel.com>, stable@dpdk.org,\n Priyalee Kushwaha <priyalee.kushwaha@intel.com>", "Subject": "[PATCH v2 03/15] common/idpf: fix ITR register definitions for AVF", "Date": "Fri, 21 Apr 2023 04:40:31 -0400", "Message-Id": "<20230421084043.135503-4-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230421084043.135503-1-wenjing.qiao@intel.com>", "References": "<20230413094502.1714755-2-wenjing.qiao@intel.com>\n <20230421084043.135503-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Fix ITR register definitions for AVF1.0 and AVF2.0\n\nFixes: fb4ac04e9bfa (\"common/idpf: introduce common library\")\nCc: stable@dpdk.org\n\nSigned-off-by: Priyalee Kushwaha <priyalee.kushwaha@intel.com>\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/common/idpf/base/idpf_lan_pf_regs.h | 9 +++++++--\n drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 ++++++++++++-----\n 2 files changed, 19 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h\nindex 3df2347bd7..7f731ec3d6 100644\n--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h\n@@ -77,8 +77,13 @@\n #define PF_GLINT_DYN_CTL_WB_ON_ITR_M\tBIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)\n #define PF_GLINT_DYN_CTL_INTENA_MSK_S\t31\n #define PF_GLINT_DYN_CTL_INTENA_MSK_M\tBIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)\n-#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start))\n-#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) * 0x1000))\n+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is\n+ * spacing b/w itrn registers of the same vector.\n+ */\n+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n+\t\t((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n+/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */\n+#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n #define PF_GLINT_ITR_MAX_INDEX\t\t2\n #define PF_GLINT_ITR_INTERVAL_S\t\t0\n #define PF_GLINT_ITR_INTERVAL_M\t\tMAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S)\ndiff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h\nindex 9cd4f757d9..13c5c5a7da 100644\n--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h\n@@ -90,11 +90,18 @@\n #define VF_INT_DYN_CTLN_WB_ON_ITR_M\tBIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)\n #define VF_INT_DYN_CTLN_INTENA_MSK_S\t31\n #define VF_INT_DYN_CTLN_INTENA_MSK_M\tBIT(VF_INT_DYN_CTLN_INTENA_MSK_S)\n-#define VF_INT_ITR0(_i)\t\t\t(0x00004C00 + ((_i) * 4))\n-#define VF_INT_ITRN_V2(_i, _reg_start)\t((_reg_start) + (((_i)) * 4))\n-#define VF_INT_ITRN(_i, _INT)\t\t(0x00002800 + ((_i) * 4) + ((_INT) * 0x40))\n-#define VF_INT_ITRN_64(_i, _INT)\t(0x00002C00 + ((_i) * 4) + ((_INT) * 0x100))\n-#define VF_INT_ITRN_2K(_i, _INT)\t(0x00072000 + ((_i) * 4) + ((_INT) * 0x100))\n+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing\n+ * b/w itrn registers of the same vector\n+ */\n+#define VF_INT_ITR0(_ITR)\t\t(0x00004C00 + ((_ITR) * 4))\n+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n+\t\t ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n+/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */\n+#define VF_INT_ITRN(_INT, _ITR)\t(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))\n+/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */\n+#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))\n+/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */\n+#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n #define VF_INT_ITRN_MAX_INDEX\t\t2\n #define VF_INT_ITRN_INTERVAL_S\t\t0\n #define VF_INT_ITRN_INTERVAL_M\t\tMAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)\n", "prefixes": [ "v2", "03/15" ] }{ "id": 126367, "url": "