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GET /api/patches/126315/?format=api
{ "id": 126315, "url": "http://patches.dpdk.org/api/patches/126315/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230420094347.523784-1-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230420094347.523784-1-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230420094347.523784-1-michaelba@nvidia.com", "date": "2023-04-20T09:43:47", "name": "[RFC] net/mlx5: add MPLS modify field support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bf001028f0ad12ea7293c615d69426c710755ab5", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230420094347.523784-1-michaelba@nvidia.com/mbox/", "series": [ { "id": 27797, "url": "http://patches.dpdk.org/api/series/27797/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27797", "date": "2023-04-20T09:43:47", "name": "[RFC] net/mlx5: add MPLS modify field support", "version": 1, "mbox": "http://patches.dpdk.org/series/27797/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126315/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/126315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=biYqAnpUxIN2iHNlrtIBumSzNCi8foaped19ot0N/nkLdafQtS0rjrdbRwsOFzteHymKY5Y6MEysajgOukC7f9TvrTY6nD10O0uEzWLxLuMoCqkCK58skNk0C4NxGB5w+fH1fLv9tbCTS6rTDQBr12DXMx0ndMSPe69zZgnjxjYIb8B9AsvdIIA5r+G2gpzoeIfegG/VAYo1I8UaOz2TtoQ/l6RnPeWLFfgsuIWYkwQUHpaMddUyuzV8s+AoMKYT9Q8ewQBjoMip13JNJUW2A2ATrouRp0vMzadRnMNSfp+1KuwCQ402UeBL8Mq/qiqVoUIMUuK5fiJKem5LrFkEHw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[RFC] net/mlx5: add MPLS modify field support", "Date": "Thu, 20 Apr 2023 12:43:47 +0300", "Message-ID": "<20230420094347.523784-1-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF0000E642:EE_|MN2PR12MB4255:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c1c4219a-50e9-4d64-d202-08db4183c76e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ric0eNL8SMUoGYlGyMsYaKwX0I0KcwiW51vcb0Lh+v8fqgIR9dCrJrrkhTfUmnO4gp1mq6Zsi6NafBdphC55DEVma6KkmhVV9bXUCG9cgCaNhITqks5l+se0CsaXp0PHEHR852F9USTn4zFkj4zVVxZNn2CWLJKSOkn08HuXnrT6QMo1i+cSphN4w7tUw9IWy8yV8RgKhd3bG/ZpotBXYovr2yXDRyuaOznf1m1N/sCEuAYsIkYl4GBxNgLpe3Xny65/cKWri1hPVHTSIl1iz8ODdq6vDdFb1G2Tu5nZsB0BLjfH3LcL2JQ5mLwlDxpi7EjhmLJvdQL0N99nDWDq0cknd7uVPgrjqgnPUCvLpdi2rH2YbeS/2oz1g/taHmGJA+j8xG/FiFMv3+KnyehMFv22wUoNpWrqbmac5D1XWaZ+GL4s9IRrRCRsqgIQeoKxywvsquDbW5DNwkOkaRFJrN+FVXhHnsAuqreTiff0eeb6QL8/Gc37aR2MUhWH8lL5f3juSbdqw92NtPzDB6yP0GpBnLDJ9m6Niiw+L7jDcLDCayjMZ40kVjpx17ScodqRae2EM3fm3weA4l+0ksnd1fuHLNhY3OM4tTqQgbMlkSJpuJ2XhWnEzF9dyuiqTHLsC1YF6TWkgKXcrnGob/nnQzMJGhHe+a4x8IIKAmW3jk0itLidmloOs1udylFYzz2f5dEV8qN+sKjV1aHQJrVF31EMfbcZUResy5FNuuOaa2FDQG0etH0GV1KyfM2YL5sG", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(346002)(136003)(39860400002)(376002)(396003)(451199021)(36840700001)(46966006)(40470700004)(186003)(6286002)(26005)(1076003)(7696005)(6666004)(426003)(107886003)(40480700001)(41300700001)(5660300002)(2906002)(316002)(47076005)(2616005)(336012)(4326008)(6916009)(70206006)(70586007)(8936002)(8676002)(82740400003)(54906003)(82310400005)(478600001)(86362001)(40460700003)(36756003)(83380400001)(36860700001)(55016003)(7636003)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Apr 2023 09:44:04.4100 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c1c4219a-50e9-4d64-d202-08db4183c76e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF0000E642.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4255", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for modify field in tunnel MPLS header.\nFor now it is supported only to copy from.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 5 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 23 +++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 16 +++++++++-------\n 3 files changed, 37 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex ed3d5efbb7..04c1400a1e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -787,6 +787,11 @@ enum mlx5_modification_field {\n \tMLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,\n \tMLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76,\n \tMLX5_MODI_HASH_RESULT = 0x81,\n+\tMLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,\n+\tMLX5_MODI_IN_MPLS_LABEL_1,\n+\tMLX5_MODI_IN_MPLS_LABEL_2,\n+\tMLX5_MODI_IN_MPLS_LABEL_3,\n+\tMLX5_MODI_IN_MPLS_LABEL_4,\n \tMLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A,\n \tMLX5_MODI_INVALID = INT_MAX,\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex f136f43b0a..93cce16a1e 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1388,6 +1388,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev,\n \tcase RTE_FLOW_FIELD_GENEVE_VNI:\n \t\treturn 24;\n \tcase RTE_FLOW_FIELD_GTP_TEID:\n+\tcase RTE_FLOW_FIELD_MPLS:\n \tcase RTE_FLOW_FIELD_TAG:\n \t\treturn 32;\n \tcase RTE_FLOW_FIELD_MARK:\n@@ -1435,6 +1436,12 @@ flow_modify_info_mask_32_masked(uint32_t length, uint32_t off, uint32_t post_mas\n \treturn rte_cpu_to_be_32(mask & post_mask);\n }\n \n+static __rte_always_inline enum mlx5_modification_field\n+mlx5_mpls_modi_field_get(const struct rte_flow_action_modify_data *data)\n+{\n+\treturn MLX5_MODI_IN_MPLS_LABEL_0 + data->sub_level;\n+}\n+\n static void\n mlx5_modify_flex_item(const struct rte_eth_dev *dev,\n \t\t const struct mlx5_flex_item *flex,\n@@ -1893,6 +1900,16 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_MPLS:\n+\t\tMLX5_ASSERT(data->offset + width <= 32);\n+\t\toff_be = 32 - (data->offset + width);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0,\n+\t\t\t\t\tmlx5_mpls_modi_field_get(data)};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_TAG:\n \t\t{\n \t\t\tMLX5_ASSERT(data->offset + width <= 32);\n@@ -5344,6 +5361,12 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifications of the GENEVE Network\"\n \t\t\t\t\" Identifier is not supported\");\n+\tif (action_modify_field->dst.field == RTE_FLOW_FIELD_MPLS ||\n+\t action_modify_field->src.field == RTE_FLOW_FIELD_MPLS)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifications of the MPLS header \"\n+\t\t\t\t\"is not supported\");\n \tif (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||\n \t action_modify_field->src.field == RTE_FLOW_FIELD_MARK)\n \t\tif (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7e0ee8d883..fd2ad3bb58 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -3546,10 +3546,8 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action,\n \t\t\t\t const struct rte_flow_action *mask,\n \t\t\t\t struct rte_flow_error *error)\n {\n-\tconst struct rte_flow_action_modify_field *action_conf =\n-\t\taction->conf;\n-\tconst struct rte_flow_action_modify_field *mask_conf =\n-\t\tmask->conf;\n+\tconst struct rte_flow_action_modify_field *action_conf = action->conf;\n+\tconst struct rte_flow_action_modify_field *mask_conf = mask->conf;\n \n \tif (action_conf->operation != mask_conf->operation)\n \t\treturn rte_flow_error_set(error, EINVAL,\n@@ -3604,6 +3602,11 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifying Geneve VNI is not supported\");\n+\t/* Due to HW bug, tunnel MPLS header is read only. */\n+\tif (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"MPLS cannot be used as destination\");\n \treturn 0;\n }\n \n@@ -4134,9 +4137,8 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,\n \t\t\taction_flags |= MLX5_FLOW_ACTION_METER;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:\n-\t\t\tret = flow_hw_validate_action_modify_field(action,\n-\t\t\t\t\t\t\t\t\tmask,\n-\t\t\t\t\t\t\t\t\terror);\n+\t\t\tret = flow_hw_validate_action_modify_field(action, mask,\n+\t\t\t\t\t\t\t\t error);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;\n", "prefixes": [ "RFC" ] }