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GET /api/patches/125909/?format=api
{ "id": 125909, "url": "http://patches.dpdk.org/api/patches/125909/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230411091144.1087887-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411091144.1087887-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411091144.1087887-4-ndabilpuram@marvell.com", "date": "2023-04-11T09:11:27", "name": "[04/21] common/cnxk: reduce sqes per sqb by one", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9aba3bac3df66d04460bd9548e2b28ef7fe3823e", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230411091144.1087887-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27660, "url": "http://patches.dpdk.org/api/series/27660/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27660", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "version": 1, "mbox": "http://patches.dpdk.org/series/27660/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125909/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/125909/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F0EDE4291B;\n\tTue, 11 Apr 2023 11:12:26 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0E97342C24;\n\tTue, 11 Apr 2023 11:12:16 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C2A1342B71\n for <dev@dpdk.org>; Tue, 11 Apr 2023 11:12:14 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33B8VpNP021637 for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:14 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1sa-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:13 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 02:12:12 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 02:12:12 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 9A5D53F7070;\n Tue, 11 Apr 2023 02:12:09 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=mlAK037H9XpavehJcWHR9ZJDJHGRk8/FLpA5BdcKPp8=;\n b=Sieg/+UwYKgRLZcSuWW/dPYTNxYjFX0HgzKpqaGZ+oePgn7bgceV3sKzRR8Ko77vdyWw\n Wjz7Hoxojbmqx4xMAOsb+nEBKpMnzyfZyjV63mcHAsM/0VpR8F+puUklmrSAOG7QIrdE\n 1HldeKfkOBNtUWcBlSyrXQvxD2daxv0dgjposunAu83GUTrtjmKs6ApXpBBpUz8uQy5m\n +gVTLgwIU2yu6SHaulUVB4A3zS1+QLs9Qyd0i9Cs1NYolhYXGfxBSV94XqI/rckAZKsH\n 1wfW2KmQ6z6uKjfSZBCwAeNbrHq92rNjosow1eUz7HpUm8CFiBfkLEOx0pSk50Q+itEq qw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n \"Shijith Thotton\" <sthotton@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 04/21] common/cnxk: reduce sqes per sqb by one", "Date": "Tue, 11 Apr 2023 14:41:27 +0530", "Message-ID": "<20230411091144.1087887-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "_y05Y-4DP4KdiMZcxxrDix0OVFdP3qe-", "X-Proofpoint-ORIG-GUID": "_y05Y-4DP4KdiMZcxxrDix0OVFdP3qe-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nEach SQB reserves last SQE to store pointer to next SQB. So\neach SQB will holds either 31 or 63 based on send descriptors\nselected.\n\nThis patch also consider sqb_slack to maintain threshold buffers\nto sync between HW and SW. Threshold will be maximum of 30% of\nqueue size or sqb_slack.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 2 +-\n drivers/common/cnxk/roc_nix_priv.h | 2 +-\n drivers/common/cnxk/roc_nix_queue.c | 21 ++++++++++-----------\n drivers/event/cnxk/cn10k_eventdev.c | 2 +-\n drivers/event/cnxk/cn9k_eventdev.c | 2 +-\n 5 files changed, 14 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 188b8800d3..50aef4fe85 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -13,7 +13,7 @@\n #define ROC_NIX_BPF_STATS_MAX\t 12\n #define ROC_NIX_MTR_ID_INVALID\t UINT32_MAX\n #define ROC_NIX_PFC_CLASS_INVALID UINT8_MAX\n-#define ROC_NIX_SQB_LOWER_THRESH 70U\n+#define ROC_NIX_SQB_THRESH\t 30U\n #define ROC_NIX_SQB_SLACK\t 12U\n \n /* Reserved interface types for BPID allocation */\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 99e27cdc56..7144d1ee10 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -12,7 +12,7 @@\n #define NIX_MAX_SQB\t ((uint16_t)512)\n #define NIX_DEF_SQB\t ((uint16_t)16)\n #define NIX_MIN_SQB\t ((uint16_t)8)\n-#define NIX_SQB_LIST_SPACE ((uint16_t)2)\n+#define NIX_SQB_PREFETCH ((uint16_t)1)\n \n /* Apply BP/DROP when CQ is 95% full */\n #define NIX_CQ_THRESH_LEVEL\t(5 * 256 / 100)\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex ac4d9856c1..d29fafa895 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -982,7 +982,7 @@ static int\n sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tuint16_t sqes_per_sqb, count, nb_sqb_bufs;\n+\tuint16_t sqes_per_sqb, count, nb_sqb_bufs, thr;\n \tstruct npa_pool_s pool;\n \tstruct npa_aura_s aura;\n \tuint64_t blk_sz;\n@@ -995,22 +995,21 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n \telse\n \t\tsqes_per_sqb = (blk_sz / 8) / 8;\n \n+\t/* Reserve One SQE in each SQB to hold pointer for next SQB */\n+\tsqes_per_sqb -= 1;\n+\n \tsq->nb_desc = PLT_MAX(512U, sq->nb_desc);\n-\tnb_sqb_bufs = sq->nb_desc / sqes_per_sqb;\n-\tnb_sqb_bufs += NIX_SQB_LIST_SPACE;\n+\tnb_sqb_bufs = PLT_DIV_CEIL(sq->nb_desc, sqes_per_sqb);\n+\tthr = PLT_DIV_CEIL((nb_sqb_bufs * ROC_NIX_SQB_THRESH), 100);\n+\tnb_sqb_bufs += NIX_SQB_PREFETCH;\n \t/* Clamp up the SQB count */\n-\tnb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count,\n-\t\t\t (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs));\n+\tnb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs));\n \n \tsq->nb_sqb_bufs = nb_sqb_bufs;\n \tsq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb);\n-\tsq->nb_sqb_bufs_adj =\n-\t\tnb_sqb_bufs -\n-\t\t(PLT_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb);\n-\tsq->nb_sqb_bufs_adj =\n-\t\t(sq->nb_sqb_bufs_adj * ROC_NIX_SQB_LOWER_THRESH) / 100;\n+\tsq->nb_sqb_bufs_adj = nb_sqb_bufs;\n \n-\tnb_sqb_bufs += roc_nix->sqb_slack;\n+\tnb_sqb_bufs += PLT_MAX(thr, roc_nix->sqb_slack);\n \t/* Explicitly set nat_align alone as by default pool is with both\n \t * nat_align and buf_offset = 1 which we don't want for SQB.\n \t */\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 071ea5a212..afd8e323b8 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -995,7 +995,7 @@ cn10k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)\n \t\t\t\t\t\t(sqes_per_sqb - 1));\n \t\ttxq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;\n \t\ttxq->nb_sqb_bufs_adj =\n-\t\t\t(ROC_NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;\n+\t\t\t((100 - ROC_NIX_SQB_THRESH) * txq->nb_sqb_bufs_adj) / 100;\n \t}\n }\n \ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 2d2985f175..b104d19b9b 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -1037,7 +1037,7 @@ cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)\n \t\t\t\t\t\t(sqes_per_sqb - 1));\n \t\ttxq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;\n \t\ttxq->nb_sqb_bufs_adj =\n-\t\t\t(ROC_NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;\n+\t\t\t((100 - ROC_NIX_SQB_THRESH) * txq->nb_sqb_bufs_adj) / 100;\n \t}\n }\n \n", "prefixes": [ "04/21" ] }