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GET /api/patches/125905/?format=api
{ "id": 125905, "url": "http://patches.dpdk.org/api/patches/125905/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230411075528.1125799-6-asekhar@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411075528.1125799-6-asekhar@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411075528.1125799-6-asekhar@marvell.com", "date": "2023-04-11T07:55:28", "name": "[5/5] mempool/cnxk: add support for exchanging mbufs between pools", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "f4753da734b2dc50f0b7d23b761a9b74d08437b0", "submitter": { "id": 2125, "url": "http://patches.dpdk.org/api/people/2125/?format=api", "name": "Ashwin Sekhar T K", "email": "asekhar@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230411075528.1125799-6-asekhar@marvell.com/mbox/", "series": [ { "id": 27659, "url": "http://patches.dpdk.org/api/series/27659/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27659", "date": "2023-04-11T07:55:23", "name": "add hwpools and support exchanging mbufs between pools", "version": 1, "mbox": "http://patches.dpdk.org/series/27659/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/125905/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/125905/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7B8E442919;\n\tTue, 11 Apr 2023 09:56:17 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BB84742C24;\n\tTue, 11 Apr 2023 09:56:08 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D64FC42D2F\n for <dev@dpdk.org>; Tue, 11 Apr 2023 09:56:06 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33ALFUBq021637 for <dev@dpdk.org>; Tue, 11 Apr 2023 00:56:06 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73ajwu-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 00:56:05 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 00:56:04 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 00:56:04 -0700", "from localhost.localdomain (unknown [10.28.36.142])\n by maili.marvell.com (Postfix) with ESMTP id E00F93F7041;\n Tue, 11 Apr 2023 00:56:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=KLim8NGB5bNGnNohPyeL+PHqbChvp5N2/67/lZmThMs=;\n b=FhoarqTvUIWB8lFA+6NsMCUS8J/0DAAl6pK6FLKeN/LhFt/+Yq1BQ4EwJt7ntEirxtw6\n XTEblk9LmYiZF6U06rBZ3SNflF7ljixAqQaKbxumxySLvFcU8G7MvoXdhueDoEtItHVh\n 4tBWROXxHoK/R0WcOYwBO6yDD0gbTjDF8bxvLn4wBAN2rCoa3w150MYeYYroZXdVahCp\n hf5oGQVO/hsjD9nQgPz+i2V5AVIU7GLL0zcXa7KLU9WIhW41Q707AHgNt1uMgRkqpyS8\n W6IsB5IlckayEHVEmWDL6xKfQyNr+tBrkJKKqOm+rpaQAW4H99zMD1QCfAqph5VdKAl7 kA==", "From": "Ashwin Sekhar T K <asekhar@marvell.com>", "To": "<dev@dpdk.org>, Ashwin Sekhar T K <asekhar@marvell.com>, Pavan Nikhilesh\n <pbhagavatula@marvell.com>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <kirankumark@marvell.com>, <psatheesh@marvell.com>,\n <anoobj@marvell.com>, <gakhil@marvell.com>, <hkalra@marvell.com>,\n <ndabilpuram@marvell.com>", "Subject": "[PATCH 5/5] mempool/cnxk: add support for exchanging mbufs between\n pools", "Date": "Tue, 11 Apr 2023 13:25:28 +0530", "Message-ID": "<20230411075528.1125799-6-asekhar@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230411075528.1125799-1-asekhar@marvell.com>", "References": "<20230411075528.1125799-1-asekhar@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "U59NyDiPpZEa818PsGofbZlsup6VVJk8", "X-Proofpoint-ORIG-GUID": "U59NyDiPpZEa818PsGofbZlsup6VVJk8", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_04,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add the following cnxk mempool PMD APIs to facilitate exchanging mbufs\nbetween pools.\n * rte_pmd_cnxk_mempool_is_hwpool() - Allows user to check whether a pool\n is hwpool or not.\n * rte_pmd_cnxk_mempool_range_check_disable() - Disables range checking on\n any rte_mempool.\n * rte_pmd_cnxk_mempool_mbuf_exchange() - Exchanges mbufs between any two\n rte_mempool where the range check is disabled.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/mempool/cnxk/cn10k_hwpool_ops.c | 63 ++++++++++++++++++++-\n drivers/mempool/cnxk/cnxk_mempool.h | 4 ++\n drivers/mempool/cnxk/meson.build | 1 +\n drivers/mempool/cnxk/rte_pmd_cnxk_mempool.h | 56 ++++++++++++++++++\n drivers/mempool/cnxk/version.map | 10 ++++\n 5 files changed, 133 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mempool/cnxk/rte_pmd_cnxk_mempool.h\n create mode 100644 drivers/mempool/cnxk/version.map", "diff": "diff --git a/drivers/mempool/cnxk/cn10k_hwpool_ops.c b/drivers/mempool/cnxk/cn10k_hwpool_ops.c\nindex 9238765155..b234481ec1 100644\n--- a/drivers/mempool/cnxk/cn10k_hwpool_ops.c\n+++ b/drivers/mempool/cnxk/cn10k_hwpool_ops.c\n@@ -3,11 +3,14 @@\n */\n \n #include <rte_mempool.h>\n+#include <rte_pmd_cnxk_mempool.h>\n \n #include \"roc_api.h\"\n #include \"cnxk_mempool.h\"\n \n-#define CN10K_HWPOOL_MEM_SIZE 128\n+#define CN10K_HWPOOL_MEM_SIZE\t 128\n+#define CN10K_NPA_IOVA_RANGE_MIN 0x0\n+#define CN10K_NPA_IOVA_RANGE_MAX 0x1fffffffffff80\n \n static int __rte_hot\n cn10k_hwpool_enq(struct rte_mempool *hp, void *const *obj_table, unsigned int n)\n@@ -197,6 +200,64 @@ cn10k_hwpool_populate(struct rte_mempool *hp, unsigned int max_objs,\n \treturn hp->size;\n }\n \n+int\n+rte_pmd_cnxk_mempool_mbuf_exchange(struct rte_mbuf *m1, struct rte_mbuf *m2)\n+{\n+\tstruct rte_mempool_objhdr *hdr;\n+\n+#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n+\tif (!(CNXK_MEMPOOL_FLAGS(m1->pool) & CNXK_MEMPOOL_F_NO_RANGE_CHECK) ||\n+\t !(CNXK_MEMPOOL_FLAGS(m2->pool) & CNXK_MEMPOOL_F_NO_RANGE_CHECK)) {\n+\t\tplt_err(\"Pools must have range check disabled\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (m1->pool->elt_size != m2->pool->elt_size ||\n+\t m1->pool->header_size != m2->pool->header_size ||\n+\t m1->pool->trailer_size != m2->pool->trailer_size ||\n+\t m1->pool->size != m2->pool->size) {\n+\t\tplt_err(\"Parameters of pools involved in exchange does not match\");\n+\t\treturn -EINVAL;\n+\t}\n+#endif\n+\tRTE_SWAP(m1->pool, m2->pool);\n+\thdr = rte_mempool_get_header(m1);\n+\thdr->mp = m1->pool;\n+\thdr = rte_mempool_get_header(m2);\n+\thdr->mp = m2->pool;\n+\treturn 0;\n+}\n+\n+int\n+rte_pmd_cnxk_mempool_is_hwpool(struct rte_mempool *mp)\n+{\n+\treturn !!(CNXK_MEMPOOL_FLAGS(mp) & CNXK_MEMPOOL_F_IS_HWPOOL);\n+}\n+\n+int\n+rte_pmd_cnxk_mempool_range_check_disable(struct rte_mempool *mp)\n+{\n+\tif (rte_pmd_cnxk_mempool_is_hwpool(mp)) {\n+\t\t/* Disable only aura range check for hardware pools */\n+\t\troc_npa_aura_op_range_set(mp->pool_id, CN10K_NPA_IOVA_RANGE_MIN,\n+\t\t\t\t\t CN10K_NPA_IOVA_RANGE_MAX);\n+\t\tCNXK_MEMPOOL_SET_FLAGS(mp, CNXK_MEMPOOL_F_NO_RANGE_CHECK);\n+\t\tmp = CNXK_MEMPOOL_CONFIG(mp);\n+\t}\n+\n+\t/* No need to disable again if already disabled */\n+\tif (CNXK_MEMPOOL_FLAGS(mp) & CNXK_MEMPOOL_F_NO_RANGE_CHECK)\n+\t\treturn 0;\n+\n+\t/* Disable aura/pool range check */\n+\troc_npa_pool_op_range_set(mp->pool_id, CN10K_NPA_IOVA_RANGE_MIN,\n+\t\t\t\t CN10K_NPA_IOVA_RANGE_MAX);\n+\tif (roc_npa_pool_range_update_check(mp->pool_id) < 0)\n+\t\treturn -EBUSY;\n+\n+\tCNXK_MEMPOOL_SET_FLAGS(mp, CNXK_MEMPOOL_F_NO_RANGE_CHECK);\n+\treturn 0;\n+}\n+\n static struct rte_mempool_ops cn10k_hwpool_ops = {\n \t.name = \"cn10k_hwpool_ops\",\n \t.alloc = cn10k_hwpool_alloc,\ndiff --git a/drivers/mempool/cnxk/cnxk_mempool.h b/drivers/mempool/cnxk/cnxk_mempool.h\nindex 4ca05d53e1..669e617952 100644\n--- a/drivers/mempool/cnxk/cnxk_mempool.h\n+++ b/drivers/mempool/cnxk/cnxk_mempool.h\n@@ -20,6 +20,10 @@ enum cnxk_mempool_flags {\n \t * This flag is set by the driver.\n \t */\n \tCNXK_MEMPOOL_F_IS_HWPOOL = RTE_BIT64(2),\n+\t/* This flag indicates whether range check has been disabled for\n+\t * the pool. This flag is set by the driver.\n+\t */\n+\tCNXK_MEMPOOL_F_NO_RANGE_CHECK = RTE_BIT64(3),\n };\n \n #define CNXK_MEMPOOL_F_MASK 0xFUL\ndiff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build\nindex ce152bedd2..e388cce26a 100644\n--- a/drivers/mempool/cnxk/meson.build\n+++ b/drivers/mempool/cnxk/meson.build\n@@ -17,5 +17,6 @@ sources = files(\n 'cn10k_hwpool_ops.c',\n )\n \n+headers = files('rte_pmd_cnxk_mempool.h')\n deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_cnxk', 'mempool']\n require_iova_in_mbuf = false\ndiff --git a/drivers/mempool/cnxk/rte_pmd_cnxk_mempool.h b/drivers/mempool/cnxk/rte_pmd_cnxk_mempool.h\nnew file mode 100644\nindex 0000000000..b040d0414f\n--- /dev/null\n+++ b/drivers/mempool/cnxk/rte_pmd_cnxk_mempool.h\n@@ -0,0 +1,56 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+/**\n+ * @file rte_pmd_cnxk.h\n+ * Marvell CNXK Mempool PMD specific functions.\n+ *\n+ **/\n+\n+#ifndef _PMD_CNXK_MEMPOOL_H_\n+#define _PMD_CNXK_MEMPOOL_H_\n+\n+#include <rte_mbuf.h>\n+#include <rte_mempool.h>\n+\n+/**\n+ * Exchange mbufs between two mempools.\n+ *\n+ * @param m1\n+ * First mbuf\n+ * @param m2\n+ * Second mbuf\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise.\n+ */\n+__rte_experimental\n+int rte_pmd_cnxk_mempool_mbuf_exchange(struct rte_mbuf *m1,\n+\t\t\t\t struct rte_mbuf *m2);\n+\n+/**\n+ * Check whether a mempool is a hwpool.\n+ *\n+ * @param mp\n+ * Mempool to check.\n+ *\n+ * @return\n+ * 1 if mp is a hwpool, 0 otherwise.\n+ */\n+__rte_experimental\n+int rte_pmd_cnxk_mempool_is_hwpool(struct rte_mempool *mp);\n+\n+/**\n+ * Disable buffer address range check on a mempool.\n+ *\n+ * @param mp\n+ * Mempool to disable range check on.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise.\n+ */\n+__rte_experimental\n+int rte_pmd_cnxk_mempool_range_check_disable(struct rte_mempool *mp);\n+\n+#endif /* _PMD_CNXK_MEMPOOL_H_ */\ndiff --git a/drivers/mempool/cnxk/version.map b/drivers/mempool/cnxk/version.map\nnew file mode 100644\nindex 0000000000..755731e3b5\n--- /dev/null\n+++ b/drivers/mempool/cnxk/version.map\n@@ -0,0 +1,10 @@\n+ DPDK_23 {\n+\tlocal: *;\n+ };\n+\n+ EXPERIMENTAL {\n+\tglobal:\n+\trte_pmd_cnxk_mempool_is_hwpool;\n+\trte_pmd_cnxk_mempool_mbuf_exchange;\n+\trte_pmd_cnxk_mempool_range_check_disable;\n+ };\n", "prefixes": [ "5/5" ] }