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GET /api/patches/123549/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 123549,
    "url": "http://patches.dpdk.org/api/patches/123549/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230209084541.2712723-8-mingxia.liu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230209084541.2712723-8-mingxia.liu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230209084541.2712723-8-mingxia.liu@intel.com",
    "date": "2023-02-09T08:45:27",
    "name": "[v5,07/21] net/cpfl: support queue release",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "25e30ebd5bb1c9a29c5080baae825e232979291e",
    "submitter": {
        "id": 2514,
        "url": "http://patches.dpdk.org/api/people/2514/?format=api",
        "name": "Liu, Mingxia",
        "email": "mingxia.liu@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230209084541.2712723-8-mingxia.liu@intel.com/mbox/",
    "series": [
        {
            "id": 26914,
            "url": "http://patches.dpdk.org/api/series/26914/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26914",
            "date": "2023-02-09T08:45:20",
            "name": "add support for cpfl PMD in DPDK",
            "version": 5,
            "mbox": "http://patches.dpdk.org/series/26914/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/123549/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/123549/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 394F341C4D;\n\tThu,  9 Feb 2023 10:43:46 +0100 (CET)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1A61742D3F;\n\tThu,  9 Feb 2023 10:43:07 +0100 (CET)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 395A442D20\n for <dev@dpdk.org>; Thu,  9 Feb 2023 10:43:05 +0100 (CET)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Feb 2023 01:43:04 -0800",
            "from dpdk-mingxial-01.sh.intel.com ([10.67.119.167])\n by orsmga008.jf.intel.com with ESMTP; 09 Feb 2023 01:43:03 -0800"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1675935785; x=1707471785;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=wIZgDqdTAsT6WoaWLxgxaUB6hfsBMziulWQO1kYPTmQ=;\n b=XpITRiwb/E0aPX33JkJnRrqm7aWZQ0nFFi3Tom9lpOB1FuYvTwMtA0zV\n oynAVrk8pMoWa2AUQYKGBaz188+KIJbXnKDWdLSz/LZ/WLJFM37CNmoMa\n eDHFln7nY3omBzDyiJQYzzKCRRoLJU8t+7KIMdBC9Dliihi7Lt2R11PK3\n nDxkQeYL9Ou7h7pTqllG+t0ahlz33peNAFC3a+UA+yp5ku+TnfiB/fs1W\n GmgEMYAUNYWtxwMp+9tDSfm55B2N81vN/EAzyOE2hct+1w16fcq1Mw1DQ\n 2YJG7p2kezxxY2G5aZBJ1f/9xVqC8OPbz0QG40iBKVLuUsFVsQWa8E/Ho A==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6500,9779,10615\"; a=\"309712343\"",
            "E=Sophos;i=\"5.97,283,1669104000\"; d=\"scan'208\";a=\"309712343\"",
            "E=McAfee;i=\"6500,9779,10615\"; a=\"697964678\"",
            "E=Sophos;i=\"5.97,283,1669104000\"; d=\"scan'208\";a=\"697964678\""
        ],
        "X-ExtLoop1": "1",
        "From": "Mingxia Liu <mingxia.liu@intel.com>",
        "To": "dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com,\n beilei.xing@intel.com",
        "Cc": "Mingxia Liu <mingxia.liu@intel.com>",
        "Subject": "[PATCH v5 07/21] net/cpfl: support queue release",
        "Date": "Thu,  9 Feb 2023 08:45:27 +0000",
        "Message-Id": "<20230209084541.2712723-8-mingxia.liu@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230209084541.2712723-1-mingxia.liu@intel.com>",
        "References": "<20230118075738.904616-1-mingxia.liu@intel.com>\n <20230209084541.2712723-1-mingxia.liu@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Add support for queue operations:\n - rx_queue_release\n - tx_queue_release\n\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c |  2 ++\n drivers/net/cpfl/cpfl_rxtx.c   | 35 ++++++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx.h   |  2 ++\n 3 files changed, 39 insertions(+)",
    "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 8ce7329b78..f59ad56db2 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -623,6 +623,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {\n \t.tx_queue_start\t\t\t= cpfl_tx_queue_start,\n \t.rx_queue_stop\t\t\t= cpfl_rx_queue_stop,\n \t.tx_queue_stop\t\t\t= cpfl_tx_queue_stop,\n+\t.rx_queue_release\t\t= cpfl_dev_rx_queue_release,\n+\t.tx_queue_release\t\t= cpfl_dev_tx_queue_release,\n \t.dev_supported_ptypes_get\t= cpfl_dev_supported_ptypes_get,\n };\n \ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex ab5383a635..aa0f6bd792 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -49,6 +49,14 @@ cpfl_tx_offload_convert(uint64_t offload)\n \treturn ol;\n }\n \n+static const struct idpf_rxq_ops def_rxq_ops = {\n+\t.release_mbufs = idpf_qc_rxq_mbufs_release,\n+};\n+\n+static const struct idpf_txq_ops def_txq_ops = {\n+\t.release_mbufs = idpf_qc_txq_mbufs_release,\n+};\n+\n static const struct rte_memzone *\n cpfl_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t      uint16_t len, uint16_t queue_type,\n@@ -177,6 +185,7 @@ cpfl_rx_split_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue *rxq,\n \tidpf_qc_split_rx_bufq_reset(bufq);\n \tbufq->qrx_tail = hw->hw_addr + (vport->chunks_info.rx_buf_qtail_start +\n \t\t\t queue_idx * vport->chunks_info.rx_buf_qtail_spacing);\n+\tbufq->ops = &def_rxq_ops;\n \tbufq->q_set = true;\n \n \tif (bufq_id == 1) {\n@@ -235,6 +244,12 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (idpf_qc_rx_thresh_check(nb_desc, rx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n+\t/* Free memory if needed */\n+\tif (dev->data->rx_queues[queue_idx] != NULL) {\n+\t\tidpf_qc_rx_queue_release(dev->data->rx_queues[queue_idx]);\n+\t\tdev->data->rx_queues[queue_idx] = NULL;\n+\t}\n+\n \t/* Setup Rx queue */\n \trxq = rte_zmalloc_socket(\"cpfl rxq\",\n \t\t\t\t sizeof(struct idpf_rx_queue),\n@@ -287,6 +302,7 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\tidpf_qc_single_rx_queue_reset(rxq);\n \t\trxq->qrx_tail = hw->hw_addr + (vport->chunks_info.rx_qtail_start +\n \t\t\t\tqueue_idx * vport->chunks_info.rx_qtail_spacing);\n+\t\trxq->ops = &def_rxq_ops;\n \t} else {\n \t\tidpf_qc_split_rx_descq_reset(rxq);\n \n@@ -399,6 +415,12 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (idpf_qc_tx_thresh_check(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n+\t/* Free memory if needed. */\n+\tif (dev->data->tx_queues[queue_idx] != NULL) {\n+\t\tidpf_qc_tx_queue_release(dev->data->tx_queues[queue_idx]);\n+\t\tdev->data->tx_queues[queue_idx] = NULL;\n+\t}\n+\n \t/* Allocate the TX queue data structure. */\n \ttxq = rte_zmalloc_socket(\"cpfl txq\",\n \t\t\t\t sizeof(struct idpf_tx_queue),\n@@ -461,6 +483,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \n \ttxq->qtx_tail = hw->hw_addr + (vport->chunks_info.tx_qtail_start +\n \t\t\tqueue_idx * vport->chunks_info.tx_qtail_spacing);\n+\ttxq->ops = &def_txq_ops;\n \ttxq->q_set = true;\n \tdev->data->tx_queues[queue_idx] = txq;\n \n@@ -674,6 +697,18 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \treturn 0;\n }\n \n+void\n+cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n+{\n+\tidpf_qc_rx_queue_release(dev->data->rx_queues[qid]);\n+}\n+\n+void\n+cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n+{\n+\tidpf_qc_tx_queue_release(dev->data->tx_queues[qid]);\n+}\n+\n void\n cpfl_stop_queues(struct rte_eth_dev *dev)\n {\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex e9b810deaa..f5882401dc 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -35,4 +35,6 @@ int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n void cpfl_stop_queues(struct rte_eth_dev *dev);\n int cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n int cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n+void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n #endif /* _CPFL_RXTX_H_ */\n",
    "prefixes": [
        "v5",
        "07/21"
    ]
}