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GET /api/patches/122976/?format=api
{ "id": 122976, "url": "http://patches.dpdk.org/api/patches/122976/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-9-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230202162537.1067595-9-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230202162537.1067595-9-michaelba@nvidia.com", "date": "2023-02-02T16:25:37", "name": "[v2,8/8] compress/mlx5: add support for LZ4 algorithm", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fb45c2e786528a2ac332a6cbf70a71ca378eaa89", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-9-michaelba@nvidia.com/mbox/", "series": [ { "id": 26766, "url": "http://patches.dpdk.org/api/series/26766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26766", "date": "2023-02-02T16:25:29", "name": "compress/mlx5: add LZ4 support", "version": 2, "mbox": "http://patches.dpdk.org/series/26766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122976/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/122976/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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support for LZ4 algorithm", "Date": "Thu, 2 Feb 2023 18:25:37 +0200", "Message-ID": "<20230202162537.1067595-9-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230202162537.1067595-1-michaelba@nvidia.com>", "References": "<20230109075838.2508039-1-michaelba@nvidia.com>\n <20230202162537.1067595-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT078:EE_|MW3PR12MB4363:EE_", "X-MS-Office365-Filtering-Correlation-Id": "712ad54c-827e-4bed-61c7-08db053a2f19", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230025)(4636009)(376002)(346002)(396003)(136003)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(83380400001)(82310400005)(426003)(2906002)(336012)(2616005)(40460700003)(6286002)(7696005)(26005)(8936002)(30864003)(36860700001)(316002)(7636003)(36756003)(1076003)(6666004)(186003)(47076005)(5660300002)(82740400003)(86362001)(40480700001)(478600001)(41300700001)(356005)(70206006)(54906003)(55016003)(6916009)(8676002)(70586007)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Feb 2023 16:26:05.7929 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 712ad54c-827e-4bed-61c7-08db053a2f19", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT078.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4363", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for decompress LZ4 algorithm for mlx5 PMD.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/compressdevs/features/mlx5.ini | 18 ++-\n doc/guides/compressdevs/mlx5.rst | 49 ++++++-\n doc/guides/rel_notes/release_23_03.rst | 4 +\n drivers/compress/mlx5/mlx5_compress.c | 150 ++++++++++++++++++----\n 4 files changed, 180 insertions(+), 41 deletions(-)", "diff": "diff --git a/doc/guides/compressdevs/features/mlx5.ini b/doc/guides/compressdevs/features/mlx5.ini\nindex 891ce47936..28b050144a 100644\n--- a/doc/guides/compressdevs/features/mlx5.ini\n+++ b/doc/guides/compressdevs/features/mlx5.ini\n@@ -4,10 +4,14 @@\n ; Supported features of 'MLX5' compression driver.\n ;\n [Features]\n-HW Accelerated = Y\n-Deflate = Y\n-Adler32 = Y\n-Crc32 = Y\n-Adler32&Crc32 = Y\n-Fixed = Y\n-Dynamic = Y\n+HW Accelerated = Y\n+Deflate = Y\n+LZ4 = Y\n+Adler32 = Y\n+Crc32 = Y\n+Adler32&Crc32 = Y\n+xxHash32 = Y\n+Fixed = Y\n+Dynamic = Y\n+LZ4 Block Checksum = Y\n+LZ4 Block Independence = Y\ndiff --git a/doc/guides/compressdevs/mlx5.rst b/doc/guides/compressdevs/mlx5.rst\nindex 37839a59e3..c834025732 100644\n--- a/doc/guides/compressdevs/mlx5.rst\n+++ b/doc/guides/compressdevs/mlx5.rst\n@@ -14,8 +14,8 @@ NVIDIA MLX5 Compress Driver\n that are now NVIDIA trademarks.\n \n The mlx5 compress driver library\n-(**librte_compress_mlx5**) provides support for **NVIDIA BlueField-2**\n-families of 25/50/100/200 Gb/s adapters.\n+(**librte_compress_mlx5**) provides support for **NVIDIA BlueField-2** and\n+**NVIDIA BlueField-3** families of 25/50/100/200 Gb/s adapters.\n \n Design\n ------\n@@ -39,11 +39,27 @@ Features\n \n Compress mlx5 PMD has support for:\n \n-Compression/Decompression algorithm:\n+- Compression\n+- Decompression\n+- DMA\n \n-* DEFLATE.\n+Algorithms\n+----------\n \n-NULL algorithm for DMA operations.\n+NULL algorithm\n+~~~~~~~~~~~~~~\n+\n+NULL algorithm is the way to perform DMA operations.\n+It works through either compress or decompress operation.\n+\n+Shareable transformation.\n+\n+Checksum generation:\n+\n+* CRC32, Adler32 and combined checksum.\n+\n+DEFLATE algorithm\n+~~~~~~~~~~~~~~~~~\n \n Huffman code type:\n \n@@ -60,11 +76,31 @@ Checksum generation:\n \n * CRC32, Adler32 and combined checksum.\n \n+LZ4 algorithm\n+~~~~~~~~~~~~~\n+\n+Support for flags:\n+\n+* ``RTE_COMP_LZ4_FLAG_BLOCK_CHECKSUM``\n+* ``RTE_COMP_LZ4_FLAG_BLOCK_INDEPENDENCE``\n+\n+Window size support:\n+\n+1KB, 2KB, 4KB, 8KB, 16KB and 32KB.\n+\n+Shareable transformation.\n+\n+Checksum generation:\n+\n+* xxHash-32 checksum.\n+\n Limitations\n -----------\n \n * Scatter-Gather, SHA and Stateful are not supported.\n * Non-compressed block is not supported in compress (supported in decompress).\n+* Compress operation is not supported by BlueField-3.\n+* LZ4 algorithm is not supported by BlueField-2.\n \n Driver options\n --------------\n@@ -75,7 +111,7 @@ for an additional list of options shared with other mlx5 drivers.\n - ``log-block-size`` parameter [int]\n \n Log of the Huffman block size in the Deflate algorithm.\n- Values from [4-15]; value x means block size is 2^x.\n+ Values from [4-15]; value x means block size is 2\\ :sup:`x`.\n The default value is 15.\n \n \n@@ -83,6 +119,7 @@ Supported NICs\n --------------\n \n * NVIDIA\\ |reg| BlueField-2 SmartNIC\n+* NVIDIA\\ |reg| BlueField-3 SmartNIC\n \n Prerequisites\n -------------\ndiff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst\nindex aedc5767ff..3d97a4611d 100644\n--- a/doc/guides/rel_notes/release_23_03.rst\n+++ b/doc/guides/rel_notes/release_23_03.rst\n@@ -86,6 +86,10 @@ New Features\n * Added support for ``RTE_COMP_CHECKSUM_XXHASH32``.\n * Added support for ``lz4`` in test-compress-perf algo options.\n \n+* **Updated NVIDIA mlx5 compress PMD.**\n+\n+ * Added LZ4 algorithm support for decompress operation.\n+\n * **Allowed test single compress operation in test-compress-perf.**\n \n Enable the application options for testing only compress and only decompress.\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 7841f57b9c..e33b58ab54 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -24,6 +24,7 @@\n #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress\n #define MLX5_COMPRESS_MAX_QPS 1024\n #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u\n+#define MLX5_COMP_NUM_SUP_ALGO 4\n \n struct mlx5_compress_devarg_params {\n \tuint32_t log_block_sz;\n@@ -43,6 +44,7 @@ struct mlx5_compress_priv {\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tstruct mlx5_uar uar;\n \tstruct rte_compressdev_config dev_config;\n+\tstruct rte_compressdev_capabilities caps[MLX5_COMP_NUM_SUP_ALGO];\n \tLIST_HEAD(xform_list, mlx5_compress_xform) xform_list;\n \trte_spinlock_t xform_sl;\n \tuint32_t log_block_sz;\n@@ -70,36 +72,16 @@ static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;\n \n int mlx5_compress_logtype;\n \n-static const struct rte_compressdev_capabilities mlx5_caps[] = {\n-\t{\n-\t\t.algo = RTE_COMP_ALGO_NULL,\n-\t\t.comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |\n-\t\t\t\t RTE_COMP_FF_CRC32_CHECKSUM |\n-\t\t\t\t RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n-\t\t\t\t RTE_COMP_FF_SHAREABLE_PRIV_XFORM,\n-\t},\n-\t{\n-\t\t.algo = RTE_COMP_ALGO_DEFLATE,\n-\t\t.comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |\n-\t\t\t\t RTE_COMP_FF_CRC32_CHECKSUM |\n-\t\t\t\t RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n-\t\t\t\t RTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n-\t\t\t\t RTE_COMP_FF_HUFFMAN_FIXED |\n-\t\t\t\t RTE_COMP_FF_HUFFMAN_DYNAMIC,\n-\t\t.window_size = {.min = 10, .max = 15, .increment = 1},\n-\t},\n-\tRTE_COMP_END_OF_CAPABILITIES_LIST()\n-};\n-\n static void\n mlx5_compress_dev_info_get(struct rte_compressdev *dev,\n \t\t\t struct rte_compressdev_info *info)\n {\n-\tRTE_SET_USED(dev);\n-\tif (info != NULL) {\n+\tif (dev != NULL && info != NULL) {\n+\t\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\n \t\tinfo->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;\n \t\tinfo->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n-\t\tinfo->capabilities = mlx5_caps;\n+\t\tinfo->capabilities = priv->caps;\n \t}\n }\n \n@@ -236,6 +218,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tqp_attr.num_of_receive_wqes = 0;\n \tqp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);\n \tqp_attr.mmo = attr->mmo_compress_qp_en || attr->mmo_dma_qp_en ||\n+\t\t attr->decomp_lz4_checksum_en ||\n+\t\t attr->decomp_lz4_no_checksum_en ||\n \t\t attr->decomp_deflate_v1_en || attr->decomp_deflate_v2_en;\n \tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,\n \t\t\t\t\tqp_attr.num_of_send_wqbbs *\n@@ -280,7 +264,11 @@ mlx5_compress_xform_validate(const struct rte_comp_xform *xform,\n \t\t\treturn -ENOTSUP;\n \t\t} else if (!attr->mmo_compress_qp_en &&\n \t\t\t !attr->mmo_compress_sq_en) {\n-\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support compress operation, maybe old FW/OFED version?\");\n+\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support compress operation.\");\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\t\tif (xform->compress.algo == RTE_COMP_ALGO_LZ4) {\n+\t\t\tDRV_LOG(ERR, \"LZ4 compression is not supported.\");\n \t\t\treturn -ENOTSUP;\n \t\t}\n \t\tif (xform->compress.level == RTE_COMP_LEVEL_NONE) {\n@@ -291,6 +279,10 @@ mlx5_compress_xform_validate(const struct rte_comp_xform *xform,\n \t\t\tDRV_LOG(ERR, \"SHA is not supported.\");\n \t\t\treturn -ENOTSUP;\n \t\t}\n+\t\tif (xform->compress.chksum == RTE_COMP_CHECKSUM_XXHASH32) {\n+\t\t\tDRV_LOG(ERR, \"xxHash32 checksum isn't supported in compress operation.\");\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n \t\tbreak;\n \tcase RTE_COMP_DECOMPRESS:\n \t\tswitch (xform->decompress.algo) {\n@@ -307,6 +299,37 @@ mlx5_compress_xform_validate(const struct rte_comp_xform *xform,\n \t\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support decompress DEFLATE algorithm, maybe old FW/OFED version?\");\n \t\t\t\treturn -ENOTSUP;\n \t\t\t}\n+\t\t\tif (xform->decompress.chksum ==\n+\t\t\t RTE_COMP_CHECKSUM_XXHASH32) {\n+\t\t\t\tDRV_LOG(ERR, \"DEFLATE algorithm doesn't support xxHash32 checksum.\");\n+\t\t\t\treturn -ENOTSUP;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTE_COMP_ALGO_LZ4:\n+\t\t\tif (!attr->decomp_lz4_no_checksum_en &&\n+\t\t\t !attr->decomp_lz4_checksum_en) {\n+\t\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support decompress LZ4 algorithm, maybe old FW/OFED version?\");\n+\t\t\t\treturn -ENOTSUP;\n+\t\t\t}\n+\t\t\tif (xform->decompress.lz4.flags &\n+\t\t\t RTE_COMP_LZ4_FLAG_BLOCK_CHECKSUM) {\n+\t\t\t\tif (!attr->decomp_lz4_checksum_en) {\n+\t\t\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support decompress LZ4 block with checksum param, maybe old FW/OFED version?\");\n+\t\t\t\t\treturn -ENOTSUP;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tif (!attr->decomp_lz4_no_checksum_en) {\n+\t\t\t\t\tDRV_LOG(ERR, \"Not enough capabilities to support decompress LZ4 block without checksum param, maybe old FW/OFED version?\");\n+\t\t\t\t\treturn -ENOTSUP;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tif (xform->decompress.chksum !=\n+\t\t\t RTE_COMP_CHECKSUM_XXHASH32 &&\n+\t\t\t xform->decompress.chksum !=\n+\t\t\t RTE_COMP_CHECKSUM_NONE) {\n+\t\t\t\tDRV_LOG(ERR, \"LZ4 algorithm supports only xxHash32 checksum.\");\n+\t\t\t\treturn -ENOTSUP;\n+\t\t\t}\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tDRV_LOG(ERR, \"Algorithm %u is not supported.\",\n@@ -383,6 +406,27 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,\n \t\tcase RTE_COMP_ALGO_DEFLATE:\n \t\t\txfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<\n \t\t\t\t\t\t\tWQE_CSEG_OPC_MOD_OFFSET;\n+\t\t\txfrm->gga_ctrl1 += WQE_GGA_DECOMP_DEFLATE <<\n+\t\t\t\t\t\t WQE_GGA_DECOMP_TYPE_OFFSET;\n+\t\t\tbreak;\n+\t\tcase RTE_COMP_ALGO_LZ4:\n+\t\t\txfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<\n+\t\t\t\t\t\t\tWQE_CSEG_OPC_MOD_OFFSET;\n+\t\t\txfrm->gga_ctrl1 += WQE_GGA_DECOMP_LZ4 <<\n+\t\t\t\t\t\t WQE_GGA_DECOMP_TYPE_OFFSET;\n+\t\t\tif (xform->decompress.lz4.flags &\n+\t\t\t RTE_COMP_LZ4_FLAG_BLOCK_CHECKSUM)\n+\t\t\t\txfrm->gga_ctrl1 +=\n+\t\t\t\t MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM <<\n+\t\t\t\t\t\t WQE_GGA_DECOMP_PARAMS_OFFSET;\n+\t\t\telse\n+\t\t\t\txfrm->gga_ctrl1 +=\n+\t\t\t\t MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM\n+\t\t\t\t\t\t<< WQE_GGA_DECOMP_PARAMS_OFFSET;\n+\t\t\tif (xform->decompress.lz4.flags &\n+\t\t\t RTE_COMP_LZ4_FLAG_BLOCK_INDEPENDENCE)\n+\t\t\t\txfrm->gga_ctrl1 += 1u <<\n+\t\t\t\t\tWQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tgoto err;\n@@ -390,7 +434,7 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,\n \t\txfrm->csum_type = xform->decompress.chksum;\n \t\tbreak;\n \tdefault:\n-\t\tDRV_LOG(ERR, \"Algorithm %u is not supported.\", xform->type);\n+\t\tDRV_LOG(ERR, \"Operation %u is not supported.\", xform->type);\n \t\tgoto err;\n \t}\n \tDRV_LOG(DEBUG, \"New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum \"\n@@ -657,6 +701,10 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,\n \t\t\t\t\t\t ((uint64_t)rte_be_to_cpu_32\n \t\t\t\t\t (opaq[idx].data[crc32_idx + 1]) << 32);\n \t\t\t\tbreak;\n+\t\t\tcase RTE_COMP_CHECKSUM_XXHASH32:\n+\t\t\t\top->output_chksum = (uint64_t)rte_be_to_cpu_32\n+\t\t\t\t\t\t (opaq[idx].v2.xxh32);\n+\t\t\t\tbreak;\n \t\t\tdefault:\n \t\t\t\tbreak;\n \t\t\t}\n@@ -720,6 +768,49 @@ mlx5_compress_handle_devargs(struct mlx5_kvargs_ctrl *mkvlist,\n \treturn 0;\n }\n \n+static void\n+mlx5_compress_fill_caps(struct mlx5_compress_priv *priv,\n+\t\t\tconst struct mlx5_hca_attr *attr)\n+{\n+\tstruct rte_compressdev_capabilities caps[] = {\n+\t\t{\n+\t\t\t.algo = RTE_COMP_ALGO_NULL,\n+\t\t\t.comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM,\n+\t\t},\n+\t\t{\n+\t\t\t.algo = RTE_COMP_ALGO_DEFLATE,\n+\t\t\t.comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n+\t\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC,\n+\t\t\t.window_size = {.min = 10, .max = 15, .increment = 1},\n+\t\t},\n+\t\t{\n+\t\t\t.algo = RTE_COMP_ALGO_LZ4,\n+\t\t\t.comp_feature_flags = RTE_COMP_FF_XXHASH32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n+\t\t\t\t\tRTE_COMP_FF_LZ4_BLOCK_INDEPENDENCE,\n+\t\t\t.window_size = {.min = 1, .max = 15, .increment = 1},\n+\t\t},\n+\t\tRTE_COMP_END_OF_CAPABILITIES_LIST()\n+\t};\n+\tpriv->caps[0] = caps[0];\n+\tpriv->caps[1] = caps[1];\n+\tif (attr->decomp_lz4_checksum_en || attr->decomp_lz4_no_checksum_en) {\n+\t\tpriv->caps[2] = caps[2];\n+\t\tif (attr->decomp_lz4_checksum_en)\n+\t\t\tpriv->caps[2].comp_feature_flags |=\n+\t\t\t\t\tRTE_COMP_FF_LZ4_BLOCK_WITH_CHECKSUM;\n+\t\tpriv->caps[3] = caps[3];\n+\t} else\n+\t\tpriv->caps[2] = caps[3];\n+}\n+\n static int\n mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \t\t\tstruct mlx5_kvargs_ctrl *mkvlist)\n@@ -740,7 +831,8 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tif (!attr->decomp_deflate_v1_en && !attr->decomp_deflate_v2_en &&\n+\tif (!attr->decomp_lz4_checksum_en && !attr->decomp_lz4_no_checksum_en &&\n+\t !attr->decomp_deflate_v1_en && !attr->decomp_deflate_v2_en &&\n \t !attr->mmo_decompress_sq_en && !attr->mmo_compress_qp_en &&\n \t !attr->mmo_compress_sq_en && !attr->mmo_dma_qp_en &&\n \t !attr->mmo_dma_sq_en) {\n@@ -763,7 +855,8 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \tcompressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n \tpriv = compressdev->data->dev_private;\n \tpriv->log_block_sz = devarg_prms.log_block_sz;\n-\tif (attr->decomp_deflate_v2_en)\n+\tif (attr->decomp_deflate_v2_en || attr->decomp_lz4_checksum_en ||\n+\t attr->decomp_lz4_no_checksum_en)\n \t\tcrc32_opaq_offset = offsetof(union mlx5_gga_compress_opaque,\n \t\t\t\t\t v2.crc32);\n \telse\n@@ -773,6 +866,7 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev,\n \tpriv->crc32_opaq_offs = crc32_opaq_offset / 4;\n \tpriv->cdev = cdev;\n \tpriv->compressdev = compressdev;\n+\tmlx5_compress_fill_caps(priv, attr);\n \tif (mlx5_devx_uar_prepare(cdev, &priv->uar) != 0) {\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n \t\treturn -1;\n", "prefixes": [ "v2", "8/8" ] }