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GET /api/patches/122975/?format=api
{ "id": 122975, "url": "http://patches.dpdk.org/api/patches/122975/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-8-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230202162537.1067595-8-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230202162537.1067595-8-michaelba@nvidia.com", "date": "2023-02-02T16:25:36", "name": "[v2,7/8] common/mlx5: add LZ4 capabilities check", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2230d82b1d0840b55ccebcf5127945681c6542ac", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-8-michaelba@nvidia.com/mbox/", "series": [ { "id": 26766, "url": "http://patches.dpdk.org/api/series/26766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26766", "date": "2023-02-02T16:25:29", "name": "compress/mlx5: add LZ4 support", "version": 2, "mbox": "http://patches.dpdk.org/series/26766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122975/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122975/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E160B41BAE;\n\tThu, 2 Feb 2023 17:26:31 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2E02A43002;\n\tThu, 2 Feb 2023 17:26:08 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2043.outbound.protection.outlook.com [40.107.220.43])\n by mails.dpdk.org (Postfix) with ESMTP id 8A62642FD0\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Akhil Goyal <gakhil@marvell.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>", "Subject": "[PATCH v2 7/8] common/mlx5: add LZ4 capabilities check", "Date": "Thu, 2 Feb 2023 18:25:36 +0200", "Message-ID": "<20230202162537.1067595-8-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230202162537.1067595-1-michaelba@nvidia.com>", "References": "<20230109075838.2508039-1-michaelba@nvidia.com>\n <20230202162537.1067595-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT078:EE_|CY5PR12MB6597:EE_", "X-MS-Office365-Filtering-Correlation-Id": "44f3fb4c-22d0-4ad0-6f1a-08db053a2e40", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n vp+rEJ1DA//+Vm95hLTsQrki2jvSz4Wy1bsTORakslm+cxP6AY1FrJ4bf4E18cmWI2wzntAQXZR+NziAWkJ/Tcn4SUeYTHmBOs8ZXcVmXWLuTGukFlVctsbz+SPSRBA8aD31LbVIRV34vB1teTCOpXIfXYx+fnRiFuHjkvcA3BlEt4NQ57KchZb2kPMOT5KSAMjD759wk1wNX7bX+4bOTzJwqH0kD2mazh1XiW7gfMQNBMujquQPLls6i0PIcqdWj1j9qYjZSSiynWrYPjSSS8SzhnYPkSZLHMY9YSnmwC9EalF+4bENx7AcX5mfqUMsb19uILs2qFCLQlszIJLiLoeBZGFr1YaSw/Kmu8cEDcAeji/EXy1EUSrNT2xWoPsVk5j68o0C3RU1UPbpfwPHSSxL8W5dzWXlxYHyqIfKJsbdGslL05vdTcLUV7IwSj5deY7oc3DF82931AILipoG32jDsMP5VD+WkIkGreAijC49eeowozvsLB9wE/YKael+0eT97elSWHsXsKi3ts0pbXSIKh3380/TuEqrU43sQHtSkZ1anCMCDV9N44nJ6CSesWEZM1qAavRC04RYt6H0yd3Po3NIn8FYMjbeEVZ+0QxhJ7oBsN8GR76kbQbWcj9tY4dx9JLBgptT4sOKnUSKca3MAQGj9O7flSS/KpDjcPtjiOMMyDooTyMu+nGscRp5kV9DtYlsQnK3xRstcgaU9w==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(346002)(396003)(136003)(39860400002)(376002)(451199018)(36840700001)(40470700004)(46966006)(336012)(83380400001)(47076005)(6666004)(316002)(2616005)(426003)(54906003)(36756003)(2906002)(82310400005)(36860700001)(7636003)(478600001)(70206006)(8676002)(70586007)(4326008)(1076003)(6286002)(26005)(186003)(7696005)(82740400003)(356005)(41300700001)(40480700001)(6916009)(86362001)(8936002)(40460700003)(55016003)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Feb 2023 16:26:04.3711 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 44f3fb4c-22d0-4ad0-6f1a-08db053a2e40", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT078.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY5PR12MB6597", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add capabilities check for LZ4 decompression algorithm.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++\n drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++++++--\n 3 files changed, 23 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex dfec4dcf1b..f30daa19c7 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -989,6 +989,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\t\t log_compress_mmo_size);\n \tattr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\tlog_decompress_mmo_size);\n+\tattr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t decompress_lz4_data_only_v2);\n+\tattr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t decompress_lz4_no_checksum_v2);\n+\tattr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\tdecompress_lz4_checksum_v2);\n \tattr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);\n \tattr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\tmini_cqe_resp_flow_tag);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex edb387e272..a82af9426d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -267,6 +267,9 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_mmo_dma:5;\n \tuint32_t log_max_mmo_compress:5;\n \tuint32_t log_max_mmo_decompress:5;\n+\tuint32_t decomp_lz4_data_only_en:1;\n+\tuint32_t decomp_lz4_no_checksum_en:1;\n+\tuint32_t decomp_lz4_checksum_en:1;\n \tuint32_t umr_modify_entity_size_disabled:1;\n \tuint32_t umr_indirect_mkey_disabled:1;\n \tuint32_t log_min_stride_wqe_sz:5;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 377cbfab87..f89af8b96b 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -578,9 +578,19 @@ struct mlx5_rdma_write_wqe {\n #define\tMLX5_OPC_MOD_MMO_DECOMP 0x3u\n #define\tMLX5_OPC_MOD_MMO_DMA 0x1u\n \n+#define WQE_GGA_DECOMP_DEFLATE 0x0u\n+#define WQE_GGA_DECOMP_LZ4 0x2u\n+\n+#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u\n+#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u\n+\n #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u\n #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u\n #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u\n+#define WQE_GGA_DECOMP_PARAMS_OFFSET 20u\n+#define WQE_GGA_DECOMP_TYPE_OFFSET 8u\n+#define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u\n+\n #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u\n #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)\n #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u\n@@ -599,7 +609,7 @@ struct mlx5_gga_wqe {\n \tuint32_t opcode;\n \tuint32_t sq_ds;\n \tuint32_t flags;\n-\tuint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */\n+\tuint32_t gga_ctrl1;\n \tuint32_t gga_ctrl2;\n \tuint32_t opaque_lkey;\n \tuint64_t opaque_vaddr;\n@@ -1434,7 +1444,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 log_dma_mmo_size[0x5];\n \tu8 reserved_at_70[0x3];\n \tu8 log_compress_mmo_size[0x5];\n-\tu8 reserved_at_78[0x3];\n+\tu8 decompress_lz4_data_only_v2[0x1];\n+\tu8 decompress_lz4_no_checksum_v2[0x1];\n+\tu8 decompress_lz4_checksum_v2[0x1];\n \tu8 log_decompress_mmo_size[0x5];\n \tu8 log_max_srq_sz[0x8];\n \tu8 log_max_qp_sz[0x8];\n", "prefixes": [ "v2", "7/8" ] }