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GET /api/patches/122972/?format=api
{ "id": 122972, "url": "http://patches.dpdk.org/api/patches/122972/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230202162537.1067595-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230202162537.1067595-3-michaelba@nvidia.com", "date": "2023-02-02T16:25:31", "name": "[v2,2/8] compress/mlx5: fix wrong output Adler-32 checksum offset", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a29c8f395587a8a1ba26a8773e77988a12f7cd68", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230202162537.1067595-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 26766, "url": "http://patches.dpdk.org/api/series/26766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26766", "date": "2023-02-02T16:25:29", "name": "compress/mlx5: add LZ4 support", "version": 2, "mbox": "http://patches.dpdk.org/series/26766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122972/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122972/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D626941BAE;\n\tThu, 2 Feb 2023 17:26:08 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0490642D9E;\n\tThu, 2 Feb 2023 17:26:00 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2051.outbound.protection.outlook.com [40.107.237.51])\n by mails.dpdk.org (Postfix) with ESMTP id 1E4DF42DBF;\n Thu, 2 Feb 2023 17:25:58 +0100 (CET)", "from DS7PR03CA0132.namprd03.prod.outlook.com (2603:10b6:5:3b4::17)\n by MN0PR12MB6055.namprd12.prod.outlook.com (2603:10b6:208:3cd::20) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Akhil Goyal <gakhil@marvell.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, <stable@dpdk.org>", "Subject": "[PATCH v2 2/8] compress/mlx5: fix wrong output Adler-32 checksum\n offset", "Date": "Thu, 2 Feb 2023 18:25:31 +0200", "Message-ID": "<20230202162537.1067595-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230202162537.1067595-1-michaelba@nvidia.com>", "References": "<20230109075838.2508039-1-michaelba@nvidia.com>\n <20230202162537.1067595-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT035:EE_|MN0PR12MB6055:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b1bec425-e57a-4ca0-3172-08db053a295d", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n J1/6geot21oxOjYlloTXbIhjS63aNJlwnwAyz8QDs6DMaI//9dTPbPBk31iTEixmT7WwBhNkSkEStMi0+3SVE/vynIsPWNYB17IM+1nTTAT9Podab65+elA/LdDbn242wyu/KWi2pisVXEZA2XziFFHiBE07D7BZuNzmPymeDfIfxA4P4uifGOCw8qCCMseZF5qycJuBm6Nwbh4yi2+yqiAr2GhrthRJkDWoE/qLsbW8ysyr+k9y/AslV1nK7PZcLu6zi81BNw7bWfWE3nHEuykC4ZpkHx1fvSSsfmjNPNMM5V3hYzItlsB6Fom9QN1x5ZZ9BtCm/gCf6osfhVvo1Mr1z6PDK3QJ9/OGkJ7SGt6ktHA4pc54UwUibxWUV9+0yUyTbcrCQCuYMJVWFRPr11dTNN9SPWK2eQBjODf9fj0qGbjBUME4saTqkjJ9tKl6e0hKMj1mkuWipqmoxmCz2OGWRzyCO+RzOW/Z17M5vPrwj4BpuviD8K2oueUwSbmExpWjC3fngH6YGl4qiapp7SswzkIEAGzrAiMPd3B88xM7QiWstp5qSpavYy+keDpE9g93Lb9CLcKQQbHMfxG3vinwceabMYU7DJAUGd520RgGPsPgSoUwbNTl4MjcI3btSestpKuX0TcwrSgnFluLD4uC2aCBDMZFTGNnTfwxMLrtoLByRRlOgc9lJha/iZfdOfBfuW3D9yCDuSDkrMgzAw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199018)(46966006)(40470700004)(36840700001)(36756003)(70586007)(478600001)(83380400001)(6916009)(8676002)(4326008)(36860700001)(7636003)(54906003)(82740400003)(82310400005)(70206006)(316002)(186003)(6286002)(26005)(6666004)(40460700003)(41300700001)(47076005)(5660300002)(1076003)(40480700001)(426003)(356005)(7696005)(2616005)(55016003)(8936002)(336012)(86362001)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Feb 2023 16:25:56.1710 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b1bec425-e57a-4ca0-3172-08db053a295d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT035.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB6055", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "After de/compress dequeue, the output checksum is copied into the op\nstructure. The \"output_checksum\" field in op structure is \"uint64_t\"\ntype, and the 32-bit checksums (CRC32, Adler-32) are copied into the\nlower 32 bits.\n\nWhen both CRC32 and Adler-32 are configured, CRC32 is copied into the\nlower 32 bits and Adler-32 into the upper 32 bits.\nHowever, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the\nupper 32 bits.\n\nThis patch updates Adler-32 output checksun to be copied into the\nlower 32 bits.\n\nFixes: f8c97babc9f4 (\"compress/mlx5: add data-path functions\")\nCc: matan@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex cadff83f27..c46fb4eb89 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,\n \t\t\t\tbreak;\n \t\t\tcase RTE_COMP_CHECKSUM_ADLER32:\n \t\t\t\top->output_chksum = (uint64_t)rte_be_to_cpu_32\n-\t\t\t\t\t (opaq[idx].adler32) << 32;\n+\t\t\t\t\t\t (opaq[idx].adler32);\n \t\t\t\tbreak;\n \t\t\tcase RTE_COMP_CHECKSUM_CRC32_ADLER32:\n \t\t\t\top->output_chksum = (uint64_t)rte_be_to_cpu_32\n", "prefixes": [ "v2", "2/8" ] }