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GET /api/patches/122848/?format=api
{ "id": 122848, "url": "http://patches.dpdk.org/api/patches/122848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-40-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-40-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-40-syalavarthi@marvell.com", "date": "2023-02-01T09:23:10", "name": "[v4,39/39] ml/cnxk: enable support for configurable ocm page", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e4a0db906b0c6eacf5979424c03f6616b8204f3e", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-40-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122848/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122848/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A043641B9D;\n\tWed, 1 Feb 2023 10:27:31 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1C53E43036;\n\tWed, 1 Feb 2023 10:24:06 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 3C03642D8B\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:29 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LRYH024189 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:28 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv6-15\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:28 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:25 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:25 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 12B443F705E;\n Wed, 1 Feb 2023 01:23:25 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=pvZgn4kxRdYl+L9s1c2aPc2L/ZY7yi+c/aOubThb2xs=;\n b=Ozj3G4For+/3szcfDu5acoU6uIntEkvKYod17xiY7j9S7/cWPa1ugu1yZR/QEgg11pFP\n 8hy3HTBmoKYyfTWAwi015rPftsNs13rTO2o0nP835Fbkmo9eUiBrPwP9cIZIRUkFLMhB\n jKptq1NhOwjXaa9y77F2Fu6gZVrhwvUWMdfIdvEPFxnWNW2TK/BXHJt3ig/gCJ52y7pz\n V/hY+x9ryQiMxTIbJUiEkqtvn1uiKVjyDj0sdHhn1wG5SUK8pEUN6wMuhkm7fgN4M85Q\n vAipWzRacmziQ3Ho2sGRnsszrh8D6rETsYz3KFmhU5A76pGkvhDFnrYAdmBN9wFXcmpY CQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 39/39] ml/cnxk: enable support for configurable ocm page", "Date": "Wed, 1 Feb 2023 01:23:10 -0800", "Message-ID": "<20230201092310.23252-40-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "IUEttlyf43eGS9Tb0UJkou-Sq4uElMvK", "X-Proofpoint-ORIG-GUID": "IUEttlyf43eGS9Tb0UJkou-Sq4uElMvK", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enabled support for configurable OCM page size. A new device\nargument \"ocm_page_size\" is added to specify the page size\nfor OCM management. Supported page sizes are 1KB, 2KB, 4KB,\n8KB and 16KB. Default page size is 16KB.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n doc/guides/mldevs/cnxk.rst | 16 +++++++++\n drivers/ml/cnxk/cn10k_ml_dev.c | 61 ++++++++++++++++++++++++++++----\n drivers/ml/cnxk/cn10k_ml_dev.h | 3 ++\n drivers/ml/cnxk/cn10k_ml_model.c | 6 ++--\n drivers/ml/cnxk/cn10k_ml_ocm.c | 18 +++++++---\n drivers/ml/cnxk/cn10k_ml_ocm.h | 14 +++-----\n drivers/ml/cnxk/cn10k_ml_ops.c | 17 ++++++---\n 7 files changed, 107 insertions(+), 28 deletions(-)", "diff": "diff --git a/doc/guides/mldevs/cnxk.rst b/doc/guides/mldevs/cnxk.rst\nindex da40336299..f7f61e8bfa 100644\n--- a/doc/guides/mldevs/cnxk.rst\n+++ b/doc/guides/mldevs/cnxk.rst\n@@ -175,6 +175,22 @@ Runtime Config Options\n With the above configuration, ML cnxk driver is configured to use ML registers\n for polling in fastpath requests.\n \n+- ``OCM page size`` (default ``16384``)\n+\n+ Option to specify the page size in bytes to be used for OCM management. Available\n+ OCM is split into multiple pages of specified sizes and the pages are allocated to\n+ the models. The parameter ``ocm_page_size`` ``devargs`` is used to specify the page\n+ size to be used.\n+\n+ Supported page sizes by the driver are 1 KB, 2 KB, 4 KB, 8 KB and 16 KB. Default\n+ page size is 16 KB.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,ocm_page_size=8192\n+\n+ With the above configuration, page size of OCM is set to 8192 bytes / 8 KB.\n+\n \n Debugging Options\n -----------------\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex a746a66849..6f9a1015a6 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -24,6 +24,7 @@\n #define CN10K_ML_OCM_ALLOC_MODE\t\t\"ocm_alloc_mode\"\n #define CN10K_ML_DEV_HW_QUEUE_LOCK\t\"hw_queue_lock\"\n #define CN10K_ML_FW_POLL_MEM\t\t\"poll_mem\"\n+#define CN10K_ML_OCM_PAGE_SIZE\t\t\"ocm_page_size\"\n \n #define CN10K_ML_FW_PATH_DEFAULT\t\t\"/lib/firmware/mlip-fw.bin\"\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1\n@@ -32,6 +33,7 @@\n #define CN10K_ML_OCM_ALLOC_MODE_DEFAULT\t\t\"lowest\"\n #define CN10K_ML_DEV_HW_QUEUE_LOCK_DEFAULT\t1\n #define CN10K_ML_FW_POLL_MEM_DEFAULT\t\t\"ddr\"\n+#define CN10K_ML_OCM_PAGE_SIZE_DEFAULT\t\t16384\n \n /* ML firmware macros */\n #define FW_MEMZONE_NAME\t\t \"ml_cn10k_fw_mz\"\n@@ -53,8 +55,12 @@ static const char *const valid_args[] = {CN10K_ML_FW_PATH,\n \t\t\t\t\t CN10K_ML_OCM_ALLOC_MODE,\n \t\t\t\t\t CN10K_ML_DEV_HW_QUEUE_LOCK,\n \t\t\t\t\t CN10K_ML_FW_POLL_MEM,\n+\t\t\t\t\t CN10K_ML_OCM_PAGE_SIZE,\n \t\t\t\t\t NULL};\n \n+/* Supported OCM page sizes: 1KB, 2KB, 4KB, 8KB and 16KB */\n+static const int valid_ocm_page_size[] = {1024, 2048, 4096, 8192, 16384};\n+\n /* Dummy operations for ML device */\n struct rte_ml_dev_ops ml_dev_dummy_ops = {0};\n \n@@ -95,12 +101,15 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \tstruct rte_kvargs *kvlist = NULL;\n \tbool ocm_alloc_mode_set = false;\n \tbool hw_queue_lock_set = false;\n+\tbool ocm_page_size_set = false;\n \tchar *ocm_alloc_mode = NULL;\n \tbool poll_mem_set = false;\n \tbool fw_path_set = false;\n \tchar *poll_mem = NULL;\n \tchar *fw_path = NULL;\n \tint ret = 0;\n+\tbool found;\n+\tuint8_t i;\n \n \tif (devargs == NULL)\n \t\tgoto check_args;\n@@ -191,6 +200,17 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t\tpoll_mem_set = true;\n \t}\n \n+\tif (rte_kvargs_count(kvlist, CN10K_ML_OCM_PAGE_SIZE) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CN10K_ML_OCM_PAGE_SIZE, &parse_integer_arg,\n+\t\t\t\t\t &mldev->ocm_page_size);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\", CN10K_ML_OCM_PAGE_SIZE);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tocm_page_size_set = true;\n+\t}\n+\n check_args:\n \tif (!fw_path_set)\n \t\tmldev->fw.path = CN10K_ML_FW_PATH_DEFAULT;\n@@ -272,6 +292,32 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t}\n \tplt_info(\"ML: %s = %s\", CN10K_ML_FW_POLL_MEM, mldev->fw.poll_mem);\n \n+\tif (!ocm_page_size_set) {\n+\t\tmldev->ocm_page_size = CN10K_ML_OCM_PAGE_SIZE_DEFAULT;\n+\t} else {\n+\t\tif (mldev->ocm_page_size < 0) {\n+\t\t\tplt_err(\"Invalid argument, %s = %d\\n\", CN10K_ML_OCM_PAGE_SIZE,\n+\t\t\t\tmldev->ocm_page_size);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tfound = false;\n+\t\tfor (i = 0; i < PLT_DIM(valid_ocm_page_size); i++) {\n+\t\t\tif (mldev->ocm_page_size == valid_ocm_page_size[i]) {\n+\t\t\t\tfound = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (!found) {\n+\t\t\tplt_err(\"Unsupported ocm_page_size = %d\\n\", mldev->ocm_page_size);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\tplt_info(\"ML: %s = %d\", CN10K_ML_OCM_PAGE_SIZE, mldev->ocm_page_size);\n+\n exit:\n \tif (kvlist)\n \t\trte_kvargs_free(kvlist);\n@@ -814,10 +860,11 @@ RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table);\n RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, \"vfio-pci\");\n \n-RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD,\n-\t\t\t CN10K_ML_FW_PATH \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE\n-\t\t\t\t\t \"=<lowest|largest>\" CN10K_ML_DEV_HW_QUEUE_LOCK\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_POLL_MEM \"=<ddr|register>\");\n+RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH\n+\t\t\t \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n+\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n+\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n+\t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE\n+\t\t\t \"=<lowest|largest>\" CN10K_ML_DEV_HW_QUEUE_LOCK\n+\t\t\t \"=<0|1>\" CN10K_ML_FW_POLL_MEM \"=<ddr|register>\" CN10K_ML_OCM_PAGE_SIZE\n+\t\t\t \"=<1024|2048|4096|8192|16384>\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 966d92e027..b4e46899c0 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -406,6 +406,9 @@ struct cn10k_ml_dev {\n \t/* Use spinlock version of ROC enqueue */\n \tint hw_queue_lock;\n \n+\t/* OCM page size */\n+\tint ocm_page_size;\n+\n \t/* JCMD enqueue function handler */\n \tbool (*ml_jcmdq_enqueue)(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd);\n \ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c\nindex 295b6f0a01..44f0087bf7 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.c\n+++ b/drivers/ml/cnxk/cn10k_ml_model.c\n@@ -339,11 +339,11 @@ cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, int16_t model_id, uin\n \t\t scratch_size, *scratch_pages);\n \n \t/* Check if the model can be loaded on OCM */\n-\tif ((*wb_pages + *scratch_pages) > ML_CN10K_OCM_NUMPAGES) {\n+\tif ((*wb_pages + *scratch_pages) > mldev->ocm.num_pages) {\n \t\tplt_err(\"Cannot create the model, OCM relocatable = %u\",\n \t\t\tmetadata->model.ocm_relocatable);\n \t\tplt_err(\"wb_pages (%u) + scratch_pages (%u) > %u\", *wb_pages, *scratch_pages,\n-\t\t\tML_CN10K_OCM_NUMPAGES);\n+\t\t\tmldev->ocm.num_pages);\n \t\treturn -ENOMEM;\n \t}\n \n@@ -352,7 +352,7 @@ cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, int16_t model_id, uin\n \t */\n \tif (!metadata->model.ocm_relocatable)\n \t\t*scratch_pages =\n-\t\t\tPLT_MAX(PLT_U64_CAST(*scratch_pages), PLT_U64_CAST(ML_CN10K_OCM_NUMPAGES));\n+\t\t\tPLT_MAX(PLT_U64_CAST(*scratch_pages), PLT_U64_CAST(mldev->ocm.num_pages));\n \n \treturn 0;\n }\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c\nindex 26e356c107..4d9e01c47b 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.c\n@@ -220,13 +220,13 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \tstruct cn10k_ml_dev *mldev;\n \tstruct cn10k_ml_ocm *ocm;\n \n-\tuint8_t local_ocm_mask[ML_CN10K_OCM_MASKWORDS] = {0};\n \tuint16_t used_scratch_pages_max;\n \tuint16_t scratch_page_start;\n \tint used_last_wb_page_max;\n \tuint16_t scratch_page_end;\n \tuint8_t search_start_tile;\n \tuint8_t search_end_tile;\n+\tuint8_t *local_ocm_mask;\n \tint wb_page_start_curr;\n \tint max_slot_sz_curr;\n \tuint8_t tile_start;\n@@ -268,6 +268,9 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \t\tsearch_end_tile = start_tile;\n \t}\n \n+\t/* nibbles + prefix '0x' */\n+\tlocal_ocm_mask = rte_zmalloc(\"local_ocm_mask\", mldev->ocm.mask_words, RTE_CACHE_LINE_SIZE);\n+\n \ttile_start = search_start_tile;\n start_search:\n \tused_scratch_pages_max = 0;\n@@ -279,7 +282,7 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \t\t\tPLT_MAX(ocm->tile_ocm_info[tile_id].last_wb_page, used_last_wb_page_max);\n \t}\n \n-\tmemset(local_ocm_mask, 0, sizeof(local_ocm_mask));\n+\tmemset(local_ocm_mask, 0, mldev->ocm.mask_words);\n \tfor (tile_id = tile_start; tile_id < tile_start + num_tiles; tile_id++) {\n \t\tfor (word_id = 0; word_id < ocm->mask_words; word_id++)\n \t\t\tlocal_ocm_mask[word_id] |= ocm->tile_ocm_info[tile_id].ocm_mask[word_id];\n@@ -332,6 +335,8 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \tif (wb_page_start != -1)\n \t\t*tilemask = GENMASK_ULL(tile_idx + num_tiles - 1, tile_idx);\n \n+\trte_free(local_ocm_mask);\n+\n \treturn wb_page_start;\n }\n \n@@ -480,7 +485,7 @@ cn10k_ml_ocm_pagemask_to_str(struct cn10k_ml_ocm_tile_info *tile_info, uint16_t\n void\n cn10k_ml_ocm_print(struct rte_ml_dev *dev, FILE *fp)\n {\n-\tchar str[ML_CN10K_OCM_NUMPAGES / 4 + 2]; /* nibbles + prefix '0x' */\n+\tchar *str;\n \tstruct cn10k_ml_dev *mldev;\n \tstruct cn10k_ml_ocm *ocm;\n \tuint8_t tile_id;\n@@ -490,12 +495,15 @@ cn10k_ml_ocm_print(struct rte_ml_dev *dev, FILE *fp)\n \tmldev = dev->data->dev_private;\n \tocm = &mldev->ocm;\n \n+\t/* nibbles + prefix '0x' */\n+\tstr = rte_zmalloc(\"ocm_mask_str\", mldev->ocm.num_pages / 4 + 2, RTE_CACHE_LINE_SIZE);\n+\n \tfprintf(fp, \"OCM State:\\n\");\n \tfor (tile_id = 0; tile_id < ocm->num_tiles; tile_id++) {\n \t\tcn10k_ml_ocm_pagemask_to_str(&ocm->tile_ocm_info[tile_id], ocm->mask_words, str);\n \n \t\twb_pages = 0 - ocm->tile_ocm_info[tile_id].scratch_pages;\n-\t\tfor (word_id = 0; word_id < ML_CN10K_OCM_MASKWORDS; word_id++)\n+\t\tfor (word_id = 0; word_id < mldev->ocm.mask_words; word_id++)\n \t\t\twb_pages +=\n \t\t\t\t__builtin_popcount(ocm->tile_ocm_info[tile_id].ocm_mask[word_id]);\n \n@@ -506,4 +514,6 @@ cn10k_ml_ocm_print(struct rte_ml_dev *dev, FILE *fp)\n \t\t\ttile_id, ocm->tile_ocm_info[tile_id].scratch_pages, wb_pages,\n \t\t\tocm->tile_ocm_info[tile_id].last_wb_page, str);\n \t}\n+\n+\trte_free(str);\n }\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h\nindex 6bf71c8da6..0ed5db98db 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.h\n@@ -8,25 +8,16 @@\n #include <rte_mldev.h>\n #include <rte_mldev_pmd.h>\n \n-/* Page size in bytes. */\n-#define ML_CN10K_OCM_PAGESIZE 0x4000\n-\n /* Number of OCM tiles. */\n #define ML_CN10K_OCM_NUMTILES 0x8\n \n /* OCM in bytes, per tile. */\n #define ML_CN10K_OCM_TILESIZE 0x100000\n \n-/* OCM pages, per tile. */\n-#define ML_CN10K_OCM_NUMPAGES (ML_CN10K_OCM_TILESIZE / ML_CN10K_OCM_PAGESIZE)\n-\n-/* Maximum OCM mask words, per tile, 8 bit words. */\n-#define ML_CN10K_OCM_MASKWORDS (ML_CN10K_OCM_NUMPAGES / 8)\n-\n /* OCM and Tile information structure */\n struct cn10k_ml_ocm_tile_info {\n \t/* Mask of used / allotted pages on tile's OCM */\n-\tuint8_t ocm_mask[ML_CN10K_OCM_MASKWORDS];\n+\tuint8_t *ocm_mask;\n \n \t/* Last pages in the tile's OCM used for weights and bias, default = -1 */\n \tint last_wb_page;\n@@ -78,6 +69,9 @@ struct cn10k_ml_ocm {\n \n \t/* OCM memory info and status*/\n \tstruct cn10k_ml_ocm_tile_info tile_ocm_info[ML_CN10K_OCM_NUMTILES];\n+\n+\t/* Memory for ocm_mask */\n+\tuint8_t *ocm_mask;\n };\n \n int cn10k_ml_ocm_tilecount(uint64_t tilemask, int *start, int *end);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 947f6a6490..4126ab4991 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -311,8 +311,8 @@ cn10k_ml_model_print(struct rte_ml_dev *dev, int16_t model_id, FILE *fp)\n \tif (model->state == ML_CN10K_MODEL_STATE_STARTED) {\n \t\tfprintf(fp, \"%*s : 0x%0*\" PRIx64 \"\\n\", FIELD_LEN, \"tilemask\",\n \t\t\tML_CN10K_OCM_NUMTILES / 4, model->model_mem_map.tilemask);\n-\t\tfprintf(fp, \"%*s : 0x%x\\n\", FIELD_LEN, \"ocm_wb_start\",\n-\t\t\tmodel->model_mem_map.wb_page_start * ML_CN10K_OCM_PAGESIZE);\n+\t\tfprintf(fp, \"%*s : 0x%\" PRIx64 \"\\n\", FIELD_LEN, \"ocm_wb_start\",\n+\t\t\tmodel->model_mem_map.wb_page_start * mldev->ocm.page_size);\n \t}\n \n \tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"num_inputs\", model->metadata.model.num_input);\n@@ -781,12 +781,18 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \tocm = &mldev->ocm;\n \tocm->num_tiles = ML_CN10K_OCM_NUMTILES;\n \tocm->size_per_tile = ML_CN10K_OCM_TILESIZE;\n-\tocm->page_size = ML_CN10K_OCM_PAGESIZE;\n+\tocm->page_size = mldev->ocm_page_size;\n \tocm->num_pages = ocm->size_per_tile / ocm->page_size;\n \tocm->mask_words = ocm->num_pages / (8 * sizeof(uint8_t));\n \n-\tfor (tile_id = 0; tile_id < ocm->num_tiles; tile_id++)\n+\t/* Allocate memory for ocm_mask */\n+\tocm->ocm_mask =\n+\t\trte_zmalloc(\"ocm_mask\", ocm->mask_words * ocm->num_tiles, RTE_CACHE_LINE_SIZE);\n+\n+\tfor (tile_id = 0; tile_id < ocm->num_tiles; tile_id++) {\n+\t\tocm->tile_ocm_info[tile_id].ocm_mask = ocm->ocm_mask + tile_id * ocm->mask_words;\n \t\tocm->tile_ocm_info[tile_id].last_wb_page = -1;\n+\t}\n \n \trte_spinlock_init(&ocm->lock);\n \n@@ -856,6 +862,9 @@ cn10k_ml_dev_close(struct rte_ml_dev *dev)\n \n \tmldev = dev->data->dev_private;\n \n+\t/* Release ocm_mask memory */\n+\trte_free(mldev->ocm.ocm_mask);\n+\n \t/* Stop and unload all models */\n \tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n \t\tmodel = dev->data->models[model_id];\n", "prefixes": [ "v4", "39/39" ] }