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GET /api/patches/122847/?format=api
{ "id": 122847, "url": "http://patches.dpdk.org/api/patches/122847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-35-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-35-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-35-syalavarthi@marvell.com", "date": "2023-02-01T09:23:05", "name": "[v4,34/39] ml/cnxk: add support to enable model data caching", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "673111b674bf57bb30061bf09b61a995470ffa85", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-35-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122847/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122847/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8ED8E41B9D;\n\tWed, 1 Feb 2023 10:27:26 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C6F1843048;\n\tWed, 1 Feb 2023 10:24:04 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C597042D75\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:28 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LRYG024189 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:28 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv6-14\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:27 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:24 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:24 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 6FD2C3F7054;\n Wed, 1 Feb 2023 01:23:23 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=cpLaHLcfPM1LlK/llSp4ouJVzNHpWuYUp8Q2468qyIc=;\n b=hcdVKo6M86Il0l7bX+FkvVS6jJ4HG9PLGh1WhNVbVHdLe3Jy1wLWodu5PVfQeB7S2yeL\n H75nYyC2LbCH75+Qj+T8JBqiF9AbAa3JWmOJaDoUl+OVxpfpagOV5xlFwPpKWFGBuifz\n hm8IIn+u061s0Q2okY/Ke+1x778DqCSX8ZDfKJIBg5af7E0PYo8PqrQOt5Uf7033Spmz\n TS6fUDDffJDZv5sSGm2YrnnFD0LiqWb3ZY3Pn8s958WbxqT4iXpfeo++6KYF/zh632ta\n WC6dwNHeSWH/AQ8PZlnR+MeCI4OFE5+PtDyvxF4E2CoI2ZGkrKffKv9w8vCI8v8qS+wg dA==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 34/39] ml/cnxk: add support to enable model data caching", "Date": "Wed, 1 Feb 2023 01:23:05 -0800", "Message-ID": "<20230201092310.23252-35-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "woAGzzfINYscG0Etisz7HEjs5aKbGGXZ", "X-Proofpoint-ORIG-GUID": "woAGzzfINYscG0Etisz7HEjs5aKbGGXZ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added device argument 'cache_model_data' to enable model data\ncaching. An inference request would be executed with dummy data\nin synchronous mode during model start stage. This run would\ncache the model weights and bias in the memory and result in\nimproved inference throughput.\n\ncache_model_data = 1, enable (default)\ncache_model_data = 0, disable\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 33 ++++++++++++++++++++--\n drivers/ml/cnxk/cn10k_ml_dev.h | 3 ++\n drivers/ml/cnxk/cn10k_ml_ops.c | 50 ++++++++++++++++++++++++++++++++++\n 3 files changed, 84 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex ac6592891b..948708a420 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -20,10 +20,12 @@\n #define CN10K_ML_FW_PATH\t\t\"fw_path\"\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS \"enable_dpe_warnings\"\n #define CN10K_ML_FW_REPORT_DPE_WARNINGS \"report_dpe_warnings\"\n+#define CN10K_ML_DEV_CACHE_MODEL_DATA\t\"cache_model_data\"\n \n #define CN10K_ML_FW_PATH_DEFAULT\t\t\"/lib/firmware/mlip-fw.bin\"\n #define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1\n #define CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT 0\n+#define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT\t1\n \n /* ML firmware macros */\n #define FW_MEMZONE_NAME\t\t \"ml_cn10k_fw_mz\"\n@@ -38,7 +40,8 @@\n #define FW_REPORT_DPE_WARNING_BITMASK BIT(1)\n \n static const char *const valid_args[] = {CN10K_ML_FW_PATH, CN10K_ML_FW_ENABLE_DPE_WARNINGS,\n-\t\t\t\t\t CN10K_ML_FW_REPORT_DPE_WARNINGS, NULL};\n+\t\t\t\t\t CN10K_ML_FW_REPORT_DPE_WARNINGS,\n+\t\t\t\t\t CN10K_ML_DEV_CACHE_MODEL_DATA, NULL};\n \n /* Dummy operations for ML device */\n struct rte_ml_dev_ops ml_dev_dummy_ops = {0};\n@@ -76,6 +79,7 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n {\n \tbool enable_dpe_warnings_set = false;\n \tbool report_dpe_warnings_set = false;\n+\tbool cache_model_data_set = false;\n \tstruct rte_kvargs *kvlist = NULL;\n \tbool fw_path_set = false;\n \tchar *fw_path = NULL;\n@@ -124,6 +128,18 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t\treport_dpe_warnings_set = true;\n \t}\n \n+\tif (rte_kvargs_count(kvlist, CN10K_ML_DEV_CACHE_MODEL_DATA) == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CN10K_ML_DEV_CACHE_MODEL_DATA, &parse_integer_arg,\n+\t\t\t\t\t &mldev->cache_model_data);\n+\t\tif (ret < 0) {\n+\t\t\tplt_err(\"Error processing arguments, key = %s\\n\",\n+\t\t\t\tCN10K_ML_DEV_CACHE_MODEL_DATA);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tcache_model_data_set = true;\n+\t}\n+\n check_args:\n \tif (!fw_path_set)\n \t\tmldev->fw.path = CN10K_ML_FW_PATH_DEFAULT;\n@@ -155,6 +171,18 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t}\n \tplt_info(\"ML: %s = %d\", CN10K_ML_FW_REPORT_DPE_WARNINGS, mldev->fw.report_dpe_warnings);\n \n+\tif (!cache_model_data_set) {\n+\t\tmldev->cache_model_data = CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT;\n+\t} else {\n+\t\tif ((mldev->cache_model_data < 0) || (mldev->cache_model_data > 1)) {\n+\t\t\tplt_err(\"Invalid argument, %s = %d\\n\", CN10K_ML_DEV_CACHE_MODEL_DATA,\n+\t\t\t\tmldev->cache_model_data);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\tplt_info(\"ML: %s = %d\", CN10K_ML_DEV_CACHE_MODEL_DATA, mldev->cache_model_data);\n+\n exit:\n \tif (kvlist)\n \t\trte_kvargs_free(kvlist);\n@@ -694,4 +722,5 @@ RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, \"vfio-pci\");\n \n RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD,\n \t\t\t CN10K_ML_FW_PATH \"=<path>\" CN10K_ML_FW_ENABLE_DPE_WARNINGS\n-\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS \"=<0|1>\");\n+\t\t\t\t\t \"=<0|1>\" CN10K_ML_FW_REPORT_DPE_WARNINGS\n+\t\t\t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA \"=<0|1>\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 9ba56ffba6..718edadde7 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -381,6 +381,9 @@ struct cn10k_ml_dev {\n \n \t/* xstats status */\n \tbool xstats_enabled;\n+\n+\t/* Enable / disable model data caching */\n+\tint cache_model_data;\n };\n \n uint64_t cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex eabb91d507..c12259f44c 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -488,6 +488,49 @@ cn10k_ml_model_xstat_reset(struct rte_ml_dev *dev, uint16_t model_id,\n \t}\n }\n \n+static int\n+cn10k_ml_cache_model_data(struct rte_ml_dev *dev, int16_t model_id)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct rte_ml_op op;\n+\n+\tchar str[RTE_MEMZONE_NAMESIZE];\n+\tconst struct plt_memzone *mz;\n+\tuint64_t isize = 0;\n+\tuint64_t osize = 0;\n+\tint ret = 0;\n+\n+\tmodel = dev->data->models[model_id];\n+\n+\t/* Create input and output buffers. */\n+\trte_ml_io_input_size_get(dev->data->dev_id, model_id, model->batch_size, &isize, NULL);\n+\trte_ml_io_output_size_get(dev->data->dev_id, model_id, model->batch_size, &osize, NULL);\n+\n+\tsnprintf(str, RTE_MEMZONE_NAMESIZE, \"%s_%d\", \"ml_dummy_io\", model_id);\n+\tmz = plt_memzone_reserve_aligned(str, isize + osize, 0, ML_CN10K_ALIGN_SIZE);\n+\tif (mz == NULL)\n+\t\treturn -ENOMEM;\n+\tmemset(mz->addr, 0, isize + osize);\n+\n+\top.model_id = model_id;\n+\top.nb_batches = model->batch_size;\n+\top.mempool = NULL;\n+\n+\top.input.addr = mz->addr;\n+\top.input.length = isize;\n+\top.input.next = NULL;\n+\n+\top.output.addr = PLT_PTR_ADD(op.input.addr, isize);\n+\top.output.length = osize;\n+\top.output.next = NULL;\n+\n+\tmemset(model->req, 0, sizeof(struct cn10k_ml_req));\n+\tret = cn10k_ml_inference_sync(dev, &op);\n+\tplt_memzone_free(mz);\n+\n+\treturn ret;\n+}\n+\n static int\n cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n {\n@@ -1467,6 +1510,13 @@ cn10k_ml_model_start(struct rte_ml_dev *dev, int16_t model_id)\n \t\t}\n \t}\n \n+\tif (ret < 0) { /* Call unload to update model and FW state, ignore error */\n+\t\trte_ml_model_stop(dev->data->dev_id, model_id);\n+\t} else {\n+\t\tif (mldev->cache_model_data && roc_model_is_cn10ka())\n+\t\t\tret = cn10k_ml_cache_model_data(dev, model_id);\n+\t}\n+\n \treturn ret;\n }\n \n", "prefixes": [ "v4", "34/39" ] }