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GET /api/patches/122834/?format=api
{ "id": 122834, "url": "http://patches.dpdk.org/api/patches/122834/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-29-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201092310.23252-29-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201092310.23252-29-syalavarthi@marvell.com", "date": "2023-02-01T09:22:59", "name": "[v4,28/39] ml/cnxk: add internal function for sync mode run", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "71354b2043b607eab6d6f056d9df0d570539c9b3", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230201092310.23252-29-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26732, "url": "http://patches.dpdk.org/api/series/26732/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26732", "date": "2023-02-01T09:22:31", "name": "Implementation of ML CNXK driver", "version": 4, "mbox": "http://patches.dpdk.org/series/26732/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122834/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 708FA41B9D;\n\tWed, 1 Feb 2023 10:26:05 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EAF2A42FD4;\n\tWed, 1 Feb 2023 10:23:47 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 2AA5342D6D\n for <dev@dpdk.org>; Wed, 1 Feb 2023 10:23:25 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3116LRY6024189 for <dev@dpdk.org>; Wed, 1 Feb 2023 01:23:24 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv5-10\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Feb 2023 01:23:24 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Wed, 1 Feb 2023 01:23:22 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Wed, 1 Feb 2023 01:23:22 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 9413D3F704D;\n Wed, 1 Feb 2023 01:23:21 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=sh8gKmQAbYJCcPY9Y8z1oR9JZnj7QzjtqvJg+vimkUk=;\n b=RpxR/LQ/WZRwGkfG4XXmsiJ6j+IBylVyZe+aKsBVKuddBWRmP+XhOpJQa3Vg+9s26IAl\n a7xeEO95n1LeQ8McxCyqz4zz94qI2D19V9zXDGIZIHKFGUQCD3LtQ75Yreh6HVjKEPop\n 3QPieFDo+xrGBPK3kPa4/ZCwLZTZ4PVi+K/60CJzDRK0QBuxibLOJk4QRXOxHkC/4iSV\n ZSPRBYFv6rEyRcQn09T9UwmcNAfflrFMAeOBIh/MEiKbNgyG5YIGyXDflfo73BNTOX09\n ubtZQcwfJc6pM6EHo4QeZBQ0FXhoa7tFcrXhSNngyWNJ0qGgtBJ23bRi25WL/R/M09ZR Rw==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v4 28/39] ml/cnxk: add internal function for sync mode run", "Date": "Wed, 1 Feb 2023 01:22:59 -0800", "Message-ID": "<20230201092310.23252-29-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230201092310.23252-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230201092310.23252-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "7fBleV9yGFxYhyZiX7IwoVMM_TtMzyDC", "X-Proofpoint-ORIG-GUID": "7fBleV9yGFxYhyZiX7IwoVMM_TtMzyDC", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added internal function to execute ML inference requests\nin synchronous mode. Sync mode inference execution is used\nto launch inference requests without using a queue-pair.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_ops.c | 53 ++++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_ops.h | 1 +\n 2 files changed, 54 insertions(+)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex ef3cbadca7..b6a35f9a4f 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -1533,6 +1533,59 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \treturn count;\n }\n \n+__rte_hot int\n+cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_req *req;\n+\tbool timeout;\n+\tint ret = 0;\n+\n+\tmldev = dev->data->dev_private;\n+\tmodel = dev->data->models[op->model_id];\n+\treq = model->req;\n+\n+\tcn10k_ml_prep_fp_job_descriptor(dev, req, op);\n+\n+\tmemset(&req->result, 0, sizeof(struct cn10k_ml_result));\n+\treq->result.user_ptr = op->user_ptr;\n+\n+\tplt_write64(ML_CN10K_POLL_JOB_START, &req->status);\n+\treq->jcmd.w1.s.jobptr = PLT_U64_CAST(&req->jd);\n+\n+\ttimeout = true;\n+\treq->timeout = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz();\n+\tdo {\n+\t\tif (roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd)) {\n+\t\t\treq->op = op;\n+\t\t\ttimeout = false;\n+\t\t\tbreak;\n+\t\t}\n+\t} while (plt_tsc_cycles() < req->timeout);\n+\n+\tif (timeout) {\n+\t\tret = -EBUSY;\n+\t\tgoto error_enqueue;\n+\t}\n+\n+\ttimeout = true;\n+\tdo {\n+\t\tif (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH) {\n+\t\t\ttimeout = false;\n+\t\t\tbreak;\n+\t\t}\n+\t} while (plt_tsc_cycles() < req->timeout);\n+\n+\tif (timeout)\n+\t\tret = -ETIME;\n+\telse\n+\t\tcn10k_ml_result_update(dev, -1, &req->result, req->op);\n+\n+error_enqueue:\n+\treturn ret;\n+}\n+\n struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Device control ops */\n \t.dev_info_get = cn10k_ml_dev_info_get,\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex 3178295bba..a17a2851b1 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -75,5 +75,6 @@ __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id\n \t\t\t\t\t struct rte_ml_op **ops, uint16_t nb_ops);\n __rte_hot uint16_t cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id,\n \t\t\t\t\t struct rte_ml_op **ops, uint16_t nb_ops);\n+__rte_hot int cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op);\n \n #endif /* _CN10K_ML_OPS_H_ */\n", "prefixes": [ "v4", "28/39" ] }